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Combinational Logic
A 2-to-1 multiplexer – WITH-SELECT-WHEN statement
s
LIBRARY ieee ;
USE ieee.std_logic_1164.all ; w0 0
f
w1 1
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
(a) Graphical symbol
f : OUT STD_LOGIC ) ;
END mux2to1 ;
LIBRARY ieee ; s
USE ieee.std_logic_1164.all ; w0 0
f
w1 1
ENTITY mux2to1 IS
PORT (w0, w1, s : IN STD_LOGIC ; (a) Graphical symbol
f : OUT STD_LOGIC ) ;
END mux2to1 ;
s f
ARCHITECTURE Behavior OF mux2to1 IS 0 w0
BEGIN 1 w1
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
s
ENTITY mux2to1 IS
w0 0
PORT ( w0, w1, s : IN STD_LOGIC ; f
f : OUT STD_LOGIC ) ; w1 1
END mux2to1 ;
(a) Graphical symbol
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
PROCESS ( w0, w1, s )
BEGIN s f
f <= w0 ;
IF s = '1' THEN 0 w0
f <= w1 ; 1 w1
END IF ;
END PROCESS ; (b) Truth table
END Behavior ;
ENTITY mux2to1 IS s
PORT ( w0, w1, s : IN STD_LOGIC ; w0 0
f : OUT STD_LOGIC ) ; f
w1 1
END mux2to1 ;
w1
w2
w3
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE mux4to1_package IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END COMPONENT ;
END mux4to1_package ;
Figure 6.28 Component declaration for the 4-to-1 multiplexer
A 16-to-1 multiplexer
s0
s1
w0
w3
w4 s2
s3
w7
w8
w11
w12
w15
ENTITY mux16to1 IS
PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;
s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END mux16to1 ;
ENTITY mux16to1 IS
PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;
s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END mux16to1 ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; En w1 w0 y0 y1 y2 y3
END dec2to4 ; 1 0 0 1 0 0 0
1 0 1 0 1 0 0
ARCHITECTURE Behavior OF dec2to4 IS 1 1 0 0 0 1 0
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; 1 1 1 0 0 0 1
BEGIN 0 x x 0 0 0 0
w0 y0 y4
w1 y1 y5
y2 y6
w2 w0 y0 y3 y7
En
w3 w1 y1
y2
En En y3 w0 y0 y8
w1 y1 y9
y2 y10
En y3 y11
w0 y0 y12
w1 y1 y13
y2 y14
En y3 y15
ENTITY dec4to16 IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 15) ) ;
END dec4to16 ;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;
ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;
ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;
z <= '1' ;
IF w = "0000" THEN z <= '0' ; END IF ;
END PROCESS ;
END Behavior ;
ENTITY compare IS
PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY compare IS
PORT ( A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
w3 w2 w1 w0 a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
Cout C(4) A B
C(3)
A B
C(2)
A B
C(1)
A B
C(0)
Co Ci Co Ci Co Ci Co Ci Cin
S S S S