Von Neumann Machine

IAS
 IAS Computer
• Developed by John Von Neumann in 1940
at Princeton University.
• In IAS computer, IAS stands for
Institute for Advanced Studies
 Organization of Von-Neumann
Machine (IAS Computer)
• The task of entering and altering programs for
ENIAC was extremely tedious
• Stored program concept – says that the
program is stored in the computer along with
any relevant data
• A stored program computer consists of a
processing unit and an attached memory
system.
Structure of Von Neumann Machine
Memory of the IAS
 1000 storage locations called words.
 Word length - 40 bits.
 A word may contain:
 A numbers stored as 40 binary digits (bits) – sign bit + 39 bit value
 An instruction-pair. Each instruction:
 An opcode (8 bits)
 An address (12 bits) – designating one of the 1000 words in memory.
Von Neumann Machine
 MBR: Memory Buffer Register
- contains the word to be stored in
memory or just received from memory. AC MQ

 MAR: Memory Address Register

- specifies the address in memory of
the word to be stored or retrieved.
MBR
 IR: Instruction Register - contains the
8-bit opcode currently being executed.
 IBR: Instruction Buffer Register
- temporary store for RHS instruction
from word in memory. IBR PC

 PC: Program Counter - address of

next instruction-pair to fetch from IR MAR
memory.
 AC: Accumulator & MQ: Multiplier
PCU
quotient - holds operands and results
of ALU ops.
 IAS Data Transfer Instructions (7)
Instruction Opcode Description
• LOAD MQ 00001010 AC ← MQ
• LOAD MQ, M(X) 00001001 MQ ← M(X)
• STOR M(X) 00100001 M(X) ← AC
• LOAD M(X) 00000001 AC ← M(X)
• LOAD – M(X) 00000010 AC ← – M(X)
• LOAD |M(X)| 00000011 AC ← |M(X)|
• LOAD – |M(X)| 00000100 AC ← – |M(X)|
 IAS Unconditional Branch
Instructions (2)
Instruction Opcode Description
• JUMP M(X,0:19) 00001101 next instruction
M(X,0:19)
• JUMP M(X,20:39) 00001110 next instruction
M(X,20:39)
 IAS Conditional Branch
Instructions (2)
Instruction Opcode Description
• JUMP +M(X,0:19) 00001111 IF AC ≥ 0,
then next
instruction
M(X,0:19)

• JUMP +M(X,20:39) 00010000 IF AC ≥ 0,

then next
instruction
M(X,20:39)
 IAS Arithmetic Instructions (8)
Instruction Opcode Description
• ADD M(X) 00000101 AC ← AC+M(X)
• ADD |M(X)| 00000111 AC ← AC+|M(X)|
• SUB M(X) 00000110 AC ← AC─M(X)
• SUB |M(X)| 00001000 AC ← AC ─ |M(X)|
• MUL M(X) 00001011 AC, MQ ← MQ×M(X)
• DIV M(X) 00001100 MQ, AC ← AC/M(X)
• LSH 00010100 AC ← AC x 2
• RSH 00010101 AC ← AC / 2
 ACAC= 7
3 MQ
MEMORY
1. LOAD M(X) 500, ADD M(X) 501
2. STOR M(X) 500, (Other Ins)
.....
500. 3
501. 4 LOAD 500
M(X)
MBR
ADD MBR =500
M(X) 43
501
(OtherSTOR
Ins) M(X)

PC 21
MAR 501
500
21
MBR LOAD
STOR
M(X)
M(X)500,
500,
3 ADD
4 (Other
M(X)
Ins)501
IR LOAD
STOR
ADD M(X)M(X)
IBR ADD
(Other
M(X) Ins)
501
AC 7
3 501
IBR
Add M(X) PC
PC←
Mar
MAR ==PC
12
←PC
LOAD M(X) 500, 3
ADD M(X) 501
4
STOR M(X) 500, (Other Ins)
IR MARadd== 501
MAR 12
501
MAR==500
MAR =500
add == 500
add
add =12
Fetch / Execute Cycle
Example of Program Execution
Instruction Cycle State Diagram
 Register transfer operation for
addition operation
1. LOAD M(X) 500, ADD M(X) 501
• Register transfer operations: (PC = 1)
– MAR ← PC
– MBR ← M[MAR]
– IBR ← MBR[20:39]
– IR ← MBR[0:7]
– MAR ← MBR[8:19]
– MBR ← M[MAR]
– AC ← MBR
– IR ← IBR[0:7]
– MAR ← IBR[8:19]
– MBR ← M[MAR]
– AC ← AC + MBR
1. On the IAS, what would the machine code
instruction look like to load the contents of
memory address 2?
Solution: Load M(X), Opcode – 00000001
Address – 000000000010
Machine code instruction:
00000001 000000000010

2. How many trips to memory does the CPU need

to make to complete this instruction during the
instruction cycle?
Solution: To fetch the instruction – 1st trip, to
fetch the operand from the given address in
the instruction – 2nd trip. So, totally 2 trips to
memory
On the IAS, describe in English the process that the CPU must
undertake to read a value from memory and to write a value to
memory in terms of what is put into the MAR, MBR, address bus,
data bus, and control bus.
Solution:
• Read:
– CPU puts the address of the value it wants into MAR.
– Read control signal is generated
– CPU puts the address on the address bus
– Memory puts the corresponding data onto data bus
– This data is then transferred to MBR.
• Write:
– CPU puts the address of the value it wants into MAR.
– CPU places the data onto the data bus
– It asserts write control signal
– Places the address onto the address bus.
– Memory transfers the data on the data bus into the corresponding
memory location.
 Re-Cap
1. ………… Register contains the 8-bit opcode instruction being
executed
2. ………………Register employed to temporarily hold the right –
hand instruction from a word in memory.

3. ………………..contains the address of the next instruction –pair

to be fetched from memory
4. …………………employed to temporarily hold operands and
results of ALU operations

5. …………………register employed to temporarily hold data and

instructions.
 Re-Cap
1.Tell an instruction of Multiplication.

2. State reason that the result of multiplication & Division

requires two memory locations
3. In a Division operation result, the quotient will be in
………register and Remainder will be in …………register.

4. In a multiplication operation result, the Most Significant 40

bits will be in ………register and least significant 40 bits will be
in …………register.

5. Tell the meaning of IAS computer Instruction ADD |M(X)|

 Size of
• AC – 40 bits
• MQ – 40 bits
• MBR – 40 bits
• IBR – 20 bits
• IR – 8 bits
• MAR – 12 bits
• PC – 12 bits
 Instruction Opcode Description
• LOAD MQ 00001010 AC ← MQ
• LOAD MQ, M(X) 00001001 MQ ←
M(X)
• STOR M(X) 00100001 M(X) ← AC
• LOAD M(X) 00000001 AC ← M(X)
• LOAD – M(X) 00000010 AC ← – M(X)
• LOAD |M(X)| 00000011 AC ← |M(X)|
• LOAD – |M(X)| 00000100 AC ← –
|M(X)|
 Instruction Opcode Description
• JUMP M(X,0:19) 00001101 next
instruction
M(X,0:19)
• JUMP M(X,20:39) 00001110 next instruction
M(X,20:39)
 Instruction Opcode Description
• JUMP +M(X,0:19) 00001111 IF AC ≥ 0,
then next
instruction
M(X,0:19)

• JUMP +M(X,20:39) 00010000 IF AC ≥ 0,

then next
instruction
M(X,20:39)
 Instruction Opcode Description
• ADD M(X) 00000101 AC ← AC+M(X)
• ADD |M(X)| 00000111 AC ← AC+|M(X)|
• SUB M(X) 00000110 AC ← AC─M(X)
• SUB |M(X)| 00001000 AC ← AC ─ |M(X)|
• MUL M(X) 00001011 AC, MQ ←
MQ×M(X)
• DIV M(X) 00001100 MQ, AC ← MQ/M(X)
• LSH 00010100 AC ← AC x 2
• RSH 00010101 AC ← AC / 2
 Instruction Opcode Description
• STOR M(X,8:19) 00010010 M(X,8:19) ←
AC(28:39)

• STOR M(X,28:39) 00010011 M(X,28:39) ←

AC(28:39)
 Class Work
• Write an assembly language program using IAS
instruction set for performing all arithmetic operations (+,
-, *, /)
• Show the register transfer operations using IAS machine
registers for multiplication operation.
• Interpret the following expression for IAS computer flow
of operations.
X=(A-B+C*(D*E-F))
Where
Data variables are available from location address 500
onwards and program can be stored at memory location
200 onwards.
 Class Work
• Write an assembly language programming for
the following code fragment and Interpret to IAS
computer flow of operations.
if(x ≥ 0)
c=a*b;
else
c=a/b;
Where
Data variables are available from location address
500 onwards and program can be stored at
memory location 200 onwards.
 Quiz
• MBR –
• MAR –
• AC –
• IBR –
• IR –
• PC –
• MQ –
• IAS –
• What is Computer Architecture?
• What is Computer Organization?
• Number of words in IAS machine?
• Number of bits per word in IAS machine?
• Data is represented in ____________ form in IAS machine
• Explain Stored program concept.
• Distinguish between Computer Architecture and Organization.
• List the characteristics of IAS computer
• In IAS computer, IAS stands for………..
 Class Work
• A two-word instruction is stored in memory at an address
designated by the symbol W. The address field of the
instruction (stored at W + 1) is designated by the symbol
Y. The operand used during the execution of the
instruction is stored at an address symbolized by Z. An
index register contains the value X. State how Z is
calculated from the other addresses if the addressing
mode of the instruction is
– Direct
– Indirect
– Relative
– Indexed
 • Assume that in a certain byte-addressed machine all
instructions are 32 bits long. Assume the following state of
affairs for the machine: Fill in the following table:

Address Value Instruction Addressing Value in R0

mode
PC 100
Load r0, #200 Immediate
R0 200 Load r0, 200 Direct
R1 300
Load r0, (200) Indirect
100 200 Load r0,r1 Register
104 300 Load r0, [r1] Register Indirect
108 400 Load r0, -100[r1] Based
200 500 Load r0, 200[PC] Relative

300 600

500 700
 Assignment
• Collect a instruction set of any processor
and categorize them based on operation.
( Note: There are 160+ processors. So
that no two students should select same
processor. )
 References
• http://www.computersciencelab.com/Co
mputerHistory/HistoryPt1.htm
• W. Stallings, Computer organization and
architecture, Prentice-Hall,2000