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 Basic Structure of Computers
2

 Basic Operational Concepts

 Bus Structures

 Performance

 Processor Clock
 Basic Performance Equation

 Clock Rate

 Performance Measurement
 Basic Operational Concepts
3

 Activity in a computer is governed by instructions.

 To perform a task, an appropriate program consisting

of a list of instructions is stored in the memory.

 Individual instructions are brought from the memory into

the processor, which executes the specified operations.

 Data to be used as operands are also stored in the

memory.
 Basic functional units of a computer
4

Arithmetic
Input and
logic

Memory

Output Control

I/O Processor
 Instruction Execution
5

 An Instruction consists of 2 parts:

1) Operation code (Opcode)
2) Operands

OPCODE OPERANDS (Eg:-ADD LOCA, R0)

 The data/operands are stored in memory.

 The individual instruction are brought from the memory
to the processor.
 Then, the processor performs the specified operation.
 Add LOCA, R0
6

Add the operand at memory location LOCA to the

operand in a register R0 in the processor.
1. Place the sum into register R0.
2. The original contents of LOCA are preserved.
3. The original contents of R0 is overwritten.
4. Instruction is fetched from the memory into the processor –
the operand at LOCA is fetched and added to the
contents of R0 – the resulting sum is stored in register R0.
 Memory

MAR MDR
Control

PC R0

Connection Between the Processor and the Memory

R1
Processor
IR

ALU
Rn - 1

n general purpose
registers

Figure 1.2. Connections between the processor and the memory.

Processor
 Registers
8

 Instruction register (IR)

 Program counter (PC)

 General-purpose register (R0 – Rn-1)

 Memory address register (MAR)

 Memory data register (MDR)

 Typical Operating Steps
9

1. Programs reside in the memory through input devices

2. PC is set to point to the first instruction
3. The contents of PC are transferred to MAR
4. A Read signal is sent to the memory
5. The first instruction is read out and loaded into MDR
6. The contents of MDR are transferred to IR
7. Decode and execute the instruction
 8. Get operands for ALU
10
1. General-purpose register
2. Memory (address to MAR – Read – MDR to ALU)
9. Perform operation in ALU
10. Store the result back
1. To general-purpose register
2. To memory (address to MAR, result to MDR – Write)
11. During the execution, PC is incremented to the next
instruction
 Bus Structures
11

 A group of lines that serves a connecting path for several

devices is called a bus.

 In addition to the lines that carry the data, the bus must
have lines for address and control purposes.

 The simplest way to interconnect functional units is to use

a single bus.
 Input Output Memory Processor

Single-bus
Figure 1.3. Single-bus structure.

12
 There are 2 types of Bus structures:
13

1) Single Bus Structure

 Because the bus can be used for only one transfer at a time, only 2
units can actively use the bus at any given time.

 Bus control lines are used to arbitrate multiple requests for use of
the bus.

Advantages:

1) Low cost

2) Flexibility for attaching peripheral devices.

 Drawbacks of the Single Bus Structure
14

 The devices connected to a bus vary widely in their

speed of operation
 Some devices are relatively slow, such as printer and
keyboard

 Some devices are considerably fast, such as optical disks

 Memory and processor units are the fastest parts of a

computer
15

 Efficient transfer mechanism thus is needed to cope

with this problem
A common approach is to include buffer registers with
the devices to hold the information during transfers.
16

2) Multiple Bus Structure

 Systems that contain multiple buses achieve more concurrency

in operations.

 Two or more transfers can be carried out at the same time.

Advantage: Better performance

Disadvantage: Increased cost

 Performance
17

1. Processor Clock
2. Basic Performance Equation
3. Clock Rate
4. Performance Measurement
 The most important measure of a computer is how quickly it can
execute programs. Three factors affect performance:
 Hardware design
 Instruction set
 Compiler
18

 Because programs are usually written in a High Level

Language, performance is also affected by the compiler that
translates programs into machine language.
 For best performance, it is necessary to design the compiler,
machine instruction set and hardware in a coordinated way.
 Processor time to execute a program depends on the
hardware involved in the execution of individual machine
instructions.
 The processor cache
19

Main Cache
memory memory Processor

Bus

 At the start of execution, all program instructions are stored

in the main-memory.
20

 As execution proceeds, instructions are fetched into the

processor, and a copy is placed in the cache memory(CPU
memory).
 Later, if the same instruction is needed a second time, it is read
directly from the cache.
 A program will be executed faster if movement of
instruction/data between the main-memory and the processor
is minimized which is achieved by using the cache.
 1. Processor Clock
21

 Processor circuits are controlled by a timing signal called a

Clock.
 The clock defines regular time intervals called Clock Cycles.
 To execute a machine instruction, the processor divides the
action to be performed into a sequence of basic steps such
that each step can be completed in one clock cycle.
22

Let P = Length of one clock cycle

R = Clock rate.

Relation between P and R is given by

R=1/P

R is measured in cycles per second.

Cycles per second is also called Hertz (Hz)

 2. Basic performance equation
23

Let T = Processor time required to executed a program.

N = Actual number of instruction executions.

S = Average number of basic steps needed to execute one machine

instruction.
R = Clock rate in cycles per second.
The program execution time is given by

T=(NXS)/R
is referred to as the basic performance equation.
24

 To achieve high performance, the computer designer must

reduce the value of T, which means reducing N and S, and
increasing R.
 The value of N is reduced if source program is compiled into fewer
machine instructions.

 The value of S is reduced if instructions have a smaller number of

basic steps to perform.

 The value of R can be increased by using a higher frequency clock.

 3. Clock Rate
25

There are 2 possibilities for increasing the clock rate R:

1) Improving the IC (integrated circuits) technology makes logic-

circuits faster.

 This reduces the time needed to compute a basic step.

 This allows the clock period P to be reduced and the clock

rate R to be increased.
26

2) Reducing the amount of processing done in one basic step also

reduces the clock period P.

 In presence of a cache, the percentage of accesses to the

main-memory is small.

 The value of T will be reduced by some factor as R is

increased . S & N are not affected.
 4. Performance Measurement
27

 The Performance Measure is the time taken by a computer to

execute a given benchmark.

 Benchmark refers to standard task used to measure how well a

processor operates.

 SPEC (System Performance Evaluation Corporation) selects &

publishes the standard programs along with their test results
for different application domains.
28

 SPEC Rating is given by

 SPEC rating = 50. The computer under test is 50 times as fast

as reference-computer.
 The test is repeated for all the programs in the SPEC suite.
 Then, the geometric mean of the results is computed.
 Machine Instructions and Programs
29

1. Memory Location and Addresses

2. Memory Operations
3. Instructions and instruction sequencing
4. Addressing Modes
5. Assembly Language
6. Basic Input and Output Operations
7. Stacks and Queues
8. Subroutines
9. Additional Instructions
10. Encoding of Machine Instructions
 Memory-locations & Addresses
30

 Memory consists of many millions of storage cells (flip-flops).

 Each cell can store a bit of information i.e. 0 or 1

 Each group of n bits is referred to as a word of information,

and n is called the word length.

 The word length can vary from 16 to 64 bits.

 A unit of 8 bits is called a byte.

31

 Accessing the memory to store or retrieve a single item of

information (word/byte) requires distinct addresses for each
item location. (It is customary to use numbers from 0 through 2k-
1 as the addresses of successive-locations in the memory).

 If 2k = no. of addressable locations; then 2k addresses

constitute the address-space of the computer.

 For example, a 24-bit address generates an address-space of

2^24 locations (16 MB).
32

n bits
 Memory consists of first word
many millions of second word
storage cells, each
of which can store 1
•
bit. •
•
 Data is usually
accessed in n-bit i th word
groups. n is called
word length. •
•
•

last word
33

 32-bit word length example

32 bits

b31 b30 b1 b0

•
•
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

34

 To retrieve information from memory, either for one word or one

byte (8-bit), addresses for each location are needed.

 A k-bit address memory has 2k memory locations, namely 0 to 2k-1,

called memory space.

 24-bit memory: 224 = 16,777,216 = 16M (1M=220)

 32-bit memory: 232 = 4G (1G=230)

 1K(kilo)=210

 1T(tera)=240
 Memory-locations & Addresses
35

1. Byte addressability

2. Big-Endian and Little-Endian Assignments

3. Word Alignment

4. Accessing Numbers, Characters and Character

Strings
 1. Byte addressability
36

 It is impractical to assign distinct addresses to individual bit

locations in the memory.

 The most practical assignment is to have successive addresses

refer to successive byte locations in the memory – byte
addressable memory.

 Byte locations have addresses 0, 1, 2, … If word length is 32

bits, then successive words are located at addresses 0, 4, 8,…
 2. Big-Endian and Little-Endian Assignments
37

 In big endian machines, first byte of binary representation of

the multibyte data-type is stored first.

 In little endian machines, last byte of binary representation of

the multibyte data-type is stored first.
 Big-Endian and Little-Endian Assignments
38

Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Byte and word addressing.

 Problem
39

 Consider a computer that has a byte-addressable memory

organized in 32 bit words according to the big endian scheme.
A program reads ASCII characters entered at a keyboard and
stores them in successive byte locations 1000 and 1004 after
the name “Johnson” has been entered.

 (ASCII codes J=4AH, o=6FH, h=68H, n=6EH,s=73H)

 Byte 1007 (shown as XX)

40

 Solution – Big Endian:

Byte contents in hex, starting at location 1000, will be 4A, 6F,
68,6E,73,6F,6E. The two words at 1000 and 1004 will be
4A6F686E and 736F6EXX.

 Solution – Little Endian:

Byte contents in hex, starting at location 1000, will be 4A, 6F, 68,
6E, 73,6F,6E. The two words at 1000 and 1004 will be
6E686F4A and XX6E6F73.
 3. Word alignment
41

 Words are said to be aligned in memory if they begin at a

byte address that is a multiple of the number of bytes in a
word.

 16-bit word: word addresses: 0, 2, 4,….

 32-bit word: word addresses: 0, 4, 8,….

 64-bit word: word addresses: 0, 8,16,….

 4. Access numbers, characters, and character
strings
42

 A number usually occupies one word. It can be accessed in the

memory by specifying its word address.
 Individual characters can be accessed by their byte address.
 The beginning of a string is indicated by giving the address of
the byte contains its first character. Successive byte locations
contain successive characters of string.
 A special control character with he meaning “end of string” or
a number indicating the length of the string in bytes can be
used as the last character.
 Memory Operation
43

 Both program instructions and data operands are stored in the

memory.
 To execute an instruction the processor control circuits must
cause the word containing the instruction to be transferred
from the memory to the processor.
 Operands and results must also be moved between the
memory and the processor.
 Thus two basic operations involving memory are Load & Store.
44

1. Load (or Read or Fetch)

 Copy the contents of a specific memory location to the processor.

 The memory content doesn’t change.

 To start the Load operation, processor send address to the
memory

2. Store (or Write)

 Transfers an item of information from the processor to a specific
memory location.
 Processor sends the address of the location together data to be
written into that location.
 Instructions and Instruction Sequencing
45

A computer must have instructions capable of performing 4 types

of operations:

1. Data transfers between the memory and the processor

registers

2. Arithmetic and logic operations on data

3. Program sequencing and control

4. I/O transfers
 Instructions and Instruction Sequencing
46

1. Register transfer notation

2. Assembly language notation
3. Basic instruction type
4. Instruction execution and straight line sequencing
5. Branching
6. Condition codes
7. Generating memory address
 1. Register Transfer Notation
47

 Identify a location by a symbolic name standing

 Memory address - LOC, A, PLACE, VAR2

 Register - R0, R1, ….

 I/O Register – DATAIN, OUTSTATUS, …

 Contents of a location are denoted by placing square brackets

around the name of the location (R1←[LOC], R3 ←[R1]+[R2])

 This type of notation is know as Register Transfer Notation (RTN)

 RHS of an RTN expression always denotes a value and LHS is the

location where the value is to be placed.
 2. Assembly Language Notation
48

 Another type of notation to represent machine instructions and

programs.

 Move LOC, R1 (“Move” means copy the contents of LOC to

R1. Move instruction has two operands.)

 Same as, R1←[LOC]

 Add R1, R2, R3

 Same as, R3 ←[R1]+[R2]

 3. Basic Instruction Types
49

 Three-Address Instructions
 ADD R2, R3,R1 R1 ← R2 + R3
 Operation Source1, Source 2, Destination
 Two-Address Instructions
 ADD R2, R1 R1 ← R1 + R2
 Operation Source, Destination
 One-Address Instructions
 ADD A AC ← AC + [A]
 A processor register Accumulator is used for this purpose.
 Problem
50

 Three address, two address and one address

representation of the statement

C[A]+[B]
51

1. Three address
Add A,B,C

2. Two address
Move B,C
Add A,C

3. One address
Load A
Add B
Store C
1.
 Problem
Give a short sequence of machine instructions for the task: “Add
the contents of memory location A to those of location B and place
the answer in location C”.

a) Only Load LOC, Ri , Store Ri, LOC and Add are available

b) Suppose that Move and Add instructions are available with

the format

Move/Add Location1, Location2, is it possible to use fewer

instructions to accomplish the task in Part a ?

If yes, give the sequence

52
 Solution
53

(a) (b) Yes;

Load A,R0 Move B,C
Load B,R1 Add A,C
Add R0,R1
Store R1,C
 Instruction Formats
54

Example: Evaluate (A+B)  (C+D)

 Three-Address
1. ADD A,B,R1 ; R1 ← M[A] + M[B]
2. ADD C,D,R2 ; R2 ← M[C] + M[D]
3. MUL R1, R2,X ; M[X] ← R1  R2
 Instruction Formats
55

Example: Evaluate (A+B)  (C+D)

 Two-Address
1. MOV A,R1 ; R1 ← M[A]
2. ADD B,R1 ; R1 ← R1 + M[B]
3. MOV C,R2 ; R2 ← M[C]
4. ADD D,R2 ; R2 ← R2 + M[D]
5. MUL R2, R1 ; R1 ← R1  R2
6. MOV R1,X ; M[X] ← R1
 Instruction Formats
56

Example: Evaluate (A+B)  (C+D)

 One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STORE X ; M[X] ← AC
 Advantages of using Registers
57

 Access to registers are much faster than memory location

because the registers are inside the processor.

 Shorter instructions

 The number of registers is smaller (e.g. 32 registers need 5

bits)

 Minimize the frequency with which data is moved back and

forth between the memory and processor registers.
 4. Instruction Execution and Straight-Line
Sequencing
58

Address Contents

i
Assumptions:
Begin execution here Move A,R0
3-instruction - One memory operand
i+4 Add B,R0 program
segment per instruction
i+8 Move R0,C
- 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word instruction
B Data for
the program
Two-phase procedure
- Instruction fetch
- Instruction execute
C

Figure : A program for C  [A] + [B].

 The program is executed as follows:
59

1) Initially, the address of the first instruction is loaded into PC.

2) Then, the processor control circuits use the information in the PC

to fetch and execute instructions, one at a time, in the order of
increasing addresses. This is called Straight-Line sequencing.

3) During the execution of each instruction, PC is incremented by

4, to point to next instruction.
 There are 2 phases for Instruction Execution:
60

1) Fetch Phase: The instruction is fetched from the memory-

location and placed in the IR.

2) Execute Phase: The contents of IR is examined to determine

which operation is to be performed. The specified-operation
is then performed by the processor.
 i Move NUM1,R0
5. Branching i+4 Add NUM2,R0
i+8 Add NUM3,R0
61
•
•
•
i + 4n - 4 Add NUMn,R0
i + 4n Move R0,SUM

•
•
•
SUM
NUM1
NUM2

•
•
•
NUMn

Figure : A straight-line program for adding n numbers.

Figure :Using a loop to add n numbers Move N,R1
Clear R0
LOOP
Determine address of
62 "Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Move R0,SUM

•
•
•
SUM
N n
NUM1
NUM2

•
•
•
NUMn
 Consider the task of adding a list of ‘n’ numbers.

63

 Number of entries in the list ‘n’ is stored in memory-location N.

 Register R1 is used as a counter to determine the number of

times the loop is executed.

 Content-location N is loaded into register R1 at the beginning

of the program.

 The Loop is a straight line sequence of instructions executed as

many times as needed.
64

 The loop starts at location LOOP and ends at the instruction

Branch>0.

 During each pass,

→ address of the next list entry is determined and

→ that entry is fetched and added to R0.

 The instruction Decrement R1 reduces the contents of R1 by 1

each time through the loop.
65

 Then Branch Instruction loads a new value into the program

counter. As a result, the processor fetches and executes the
instruction at this new address called the Branch Target.

 A Conditional Branch Instruction causes a branch only if a

specified condition is satisfied. If the condition is not satisfied,
the PC is incremented in the normal way, and the next
instruction in sequential address order is fetched and executed.
 6. Condition Codes
66

 Condition code flags

The processor keeps track of information about the results
of various operations for use by subsequent conditional branch
instructions. Information is recorded in individual bits called
Condition code flags.
 Condition code register / status register
Condition code flags are usually grouped together in a
special register called Condition code register / status register.
67

Four commonly used flags are:

 N (negative) set to 1 if result is negative else 0
 Z (zero) set to 1 if result is zero else 0
 V (overflow) set to 1 if arithmetic overflow occurs else 0
 C (carry) set to 1 if carry out results from the operation
else 0
 Different instructions affect different flags. (here the branch is
taken if neither N nor Z is 1)
 7. Generating memory address
68

 The purpose of the instruction block at LOOP is to add a

different number from the list during each pass through the
loop.

 The memory operand address cannot be given directly in a

single Add instruction in the loop.

 Instruction set of a computer provides a number of such

methods called addressing modes.
 Addressing Modes
69

The different ways in which the location of an operand is

specified in an instruction are referred to as addressing modes.

1. Implementation of variables and constants

2. Indirection and pointers

3. Indexing and arrays

4. Relative addressing

5. Additional modes
 1. Implementation of variables and constants
70

 In assembly language variable is represented by allocating a register

or memory-location to hold its value.

 There are 2 accessing modes to access the variables:

1) Register Mode : The operand is the contents of a

processor register.

2) Absolute Mode (Direct Mode) : The operand is in a memory

location

 The instruction Move LOC,R2 uses these two modes.

71

 Address and data constants can be represented in assembly

language using the Immediate mode.

 Immediate mode: The operand is given explicitly in the instruction.

 A common convention is to use the sharp sign (#) in front of the

value to indicate that this value is to be used as an immediate
operand.

Move #200,R0

 Instructions for A=B+6 ?

72

A=B+6

Move B,R1

Add #6,R1

Move R1,A
 2. Indirection and Pointers
73

 Instruction provides information from which the memory

address of the operand can be determined. This address is
called effective address.

 Indirect mode : The effective address of the operand is the

contents of a register or memory location whose address
appears in the instruction.
74

 The register or memory location that contains the address of

an operand is called a pointer.

 Indirection is denoted by placing the name of the register or

memory location given in the instruction in parentheses.

Add (R1),R0

Add (A),R0
75

Indirect addressing through a Indirect addressing through a

general purpose register memory location

Add (R1),R0 Add (A),R0

Main
memory Main
B Operand A B memory

B Operand
R1 B Register
 Program :-Sum of N numbers using Indirect addressing
76
77

 Register R2 is used as a pointer to the numbers in the list, and

the operands are accessed indirectly through R2.
 The initialization-section of the program loads the counter-
value ‘n’ from memory location N into R1 and uses the
immediate addressing mode to place the address value
NUM1, which is the address of the first number in the list, into
R2.
 Then it clears R0 to 0.
78

 The first two instructions in the loop implement the unspecified

instruction block starting at LOOP.
 The first time through the loop, the instruction Add(R2),R0
fetches the operand at location NUM1 and adds it to R0.
 The second Add instruction adds 4 to the contents of the
pointer R2 , so that it will contain the address value NUM2
when the above instruction is executed in the second pass
through the loop.
 3. Indexing and Arrays
79

 Index mode – The effective address of the operand is

generated by adding a constant value to the contents of a
register.

 The register used may be a special register or any one of a

set of general-purpose register. It is referred to as an index
register.

 Symbolic representation of index mode is X(Ri).

Effective Address= X + [Ri]

80

 X denotes the constant value contained in the instruction and Ri

is the name of the register involved.

 The index register Ri contains the address of a memory

location and the value X defines an offset (displacement) from
this address to the location where the operand is found.

 The contents of the index register are not changed in the

process of generating the effective address.

Eg:- Add 20(R1), R2

 Indexed Addressing: Offset is given as a constant
81

Add 20(R1),R2

1000 1000 R1

20=offset

1020 Operand
 Indexed Addressing: Offset is in the index register
82

Add 1000(R1),R2

1000 20 R1

20=offset

1020 Operand
 Example:-
83

 A list of test scores for students taking a given course is

beginning at location LIST.
 A four word memory block comprises a record that stores the
relevant information for each student.
 Each record consists of the student’s ID followed by the scores
the student earned on three tests.
 There are ‘n’ students in the class and the value n is stored in
location N.
 Find the sum of all scores obtained on each of the tests and store
these three sums in memory location SUM1, SUM2, SUM3.
84

.
.
.
 Program:-
85
 Variations of Index Mode
86

 Index mode uses 2 registers which can be denoted as (Ri, Rj)

 Here, a second register may be used to contain the offset X.

The second register is usually called the base register.

 The effective-address of the operand is given by

EA=[Ri]+[Rj]

 This form of indexed addressing provides more flexibility in

accessing operands because both components of the
effective-address can be changed.
87

 Another version of the Index mode uses 2 registers plus a

constant, which can be denoted as X(Ri, Rj)

 The effective-address of the operand is given by EA=X+[Ri]+[Rj]

 This added flexibility is useful in accessing multiple components

inside each item in a record

 This mode implements a 3-dimensional array.

 4. Relative Addressing
88

 Relative mode – the effective address is determined by the Index

mode using the program counter in place of the general-purpose
register.

 X(PC) can be used to address a memory location that is X bytes

away from the location pointed to by the program counter.

 Since the addressed location is identified ‘relative’ to the

program counter, the name relative mode is associated with this
type of addressing.
89

 Most common use of relative mode is to specify the target

address in branch instruction.

Branch>0 LOOP

 This location is computed by specifying it as an offset from the

current value of PC.

 Branch target may be either before or after the branch

instruction, the offset is given as a signed number.
 5. Additional Modes
90

 Autoincrement mode – the effective address of the operand is

the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.

 Autoincrement mode is denoted by putting the register in

parentheses followed by a plus sign. (Ri)+

 The increment is 1 for byte-sized operands, 2 for 16-bit

operands, and 4 for 32-bit operands.
 Program to find Sum of N numbers using Autoincrement
mode
91

Move N,R1

Move #NUM1,R2 Initialization

Clear R0

LOOP Add (R2)+,R0

Decrement R1

Branch>0 LOOP

Move R0,SUM
92

 Autodecrement mode – the contents of this register specified in

the instruction are first automatically decremented and are then
used as the effective address of the operand.

 Autodecrement mode is denoted by putting the register in

parentheses preceded by a minus sign. -(Ri)
 Assembly Language
93

 Machine instructions are represented by patterns of 0’s and 1’s.

 We generally use symbolic names to write a program:

mnemonics

E.g. : MOV, ADD, INC, BR, R1

 A complete set of such symbolic names and rules for their use
constitute a programming language, referred to as an assembly
language.
94

 The set of rules for using the mnemonics in the specification of

complete instructions and programs is called the syntax of the
language.

 Programs written in an assembly language can be automatically

translated into a sequence of machine instructions by a program
called an Assembler.
95

 The user program in its original alphanumeric text format is

called a Source program, and the assembled machine language
program is called an Object Program.
Examples:
 In Absolute mode a numerical value or name used by itself.
A sharp sign is used to denote an immediate operand.
 Indirect addressing is usually specified by putting
parentheses around the name or a symbol denoting the
pointer.
 Assembly Language
96

1. Assembler Directives

2. Assembly and Execution of Programs

3. Number Notation
 1. Assembler Directives
97

 Directives are the assembler commands to the assembler

concerning the program being assembled.

 These commands are not translated into machine opcode in the

object-program.

 EQU informs the assembler about the value of an identifier

 Ex: SUM EQU 200; informs assembler that the name SUM
should be replaced by the value 200.
98

 ORIGIN tells the assembler about the starting-address of

memory-area to place the data block that follows.

 Ex: ORIGIN 204 ;Instructs assembler to initiate data-block

at memory-locations starting from 204.

 RESERVE directive is used to reserve a block of memory.

 Ex: NUM1 RESERVE 400 ;declares a memory-block of 400

bytes is to be reserved for data.
99

 END directive tells the assembler that this is the end of the
source-program text.

 RETURN directive identifies the point at which execution of the

program should be terminated.

 Any statement that makes instructions or data being placed in a

memory-location may be given a label. The label(say N or
NUM1) is assigned a value equal to the address of that
location.
 General format Of a Statement
100

Most assembly languages require statements in a source program

to be written in the form:

Label Operation Operands Comment

1. Label is an optional name associated with the memory-

address where the machine language instruction produced
from the statement will be loaded.
101

2. Operation Field contains the OP-code mnemonic of the

desired instruction or assembler.

3. Operand Field contains addressing information for accessing

one or more operands, depending on the type of instruction.

4. Comment Field is used for documentation purposes to make

program easier to understand.
 Assembly language representation for the Program to find
Sum of N numbers
102
 2. Assembly and Execution of Programs
103

 Programs written in an assembly language are automatically

translated into a sequence of machine instructions by the
Assembler.

 Assembler Program replaces all symbols denoting operations &

addressing-modes with binary-codes used in machine instructions.

→ replaces all names and labels with their actual values.

→ assigns addresses to instructions & data blocks, starting at

address given in ORIGIN directive
104

→ inserts constants that may be given in DATAWORD directives.

→ reserves memory-space as requested by RESERVE directives.

Two Pass Assembler has 2 passes:

First Pass: Work out all the addresses of labels.

As the assembler scans through a source-program, it keeps

track of all names of numerical- values that correspond to them in
a symbol-table. During the first pass, it creates a complete symbol
table.
105

Second Pass: Generate machine code, substituting values for the

labels.

 When a name appears a second time in the source-program,

it is replaced with its value from the table.

 The assembler stores the object-program on a magnetic-disk.

The object-program must be loaded into the memory of the
computer before it is executed. For this, a Loader Program is
used.
106

 Debugger Program is used to help the user find the

programming errors.

 Debugger program enables the user

 to stop execution of the object-program at some points of

interest &

 to examine the contents of various processor-registers and

memory-location.
 3. Number Notation
107

 Most assemblers allow numerical values to be specified in different

ways, using conventions that are defined by the assembly language
syntax.

 For example if the value to be used as an immediate operand it can

be given as a decimal number.

Add #93,R1

 Binary numbers can be written more compactly as hexadecimal or

hex in which 4 bits are represented by a single hex digit.

(Ex:- 1010 - A)
 Basic Input/output Operations
108

 We have seen instructions to:

 Transfer information between the processor and the

memory.

 Perform arithmetic and logic operations

 Program sequencing and flow control.

 Input/output operations which transfer data from the processor

or memory to and from the real world are essential.
109

 In general, the rate of transfer from any input device to the

processor, or from the processor to any output device is likely
to be slower than the speed of a processor.

 The difference in speed makes it necessary to create

mechanisms to synchronize the data transfer between
them.

 Let us consider a simple task of reading a character from a

keyboard and displaying that character on a display screen.
110

 A simple way of performing the task is called program-

controlled I/O.

 There are two separate blocks of instructions in the I/O

program that perform this task:

 One block of instructions transfers the character into the

processor.

 Another block of instructions causes the character to be

displayed.
 Bus

111
Processor
DATAIN DATAOUT

SIN SOUT

keyboard Display

Input:
•When a key is struck on the keyboard, an 8-bit character code is stored in the buffer
register DATAIN.
•A status control flag SIN is set to 1 to indicate that a valid character is in DATAIN.
•A program monitors SIN, and when SIN is set to 1, it reads the contents of DATAIN.
•When the character is transferred to the processor, SIN is automatically cleared.
•Initial state of SIN is 0.
 Bus

112
Processor
DATAIN DATAOUT

SIN SOUT

keyboard Display

Output:
•When SOUT is equal to 1, the display is ready to receive a character.
•A program monitors SOUT, and when SOUT is set to 1, the processor transfers a
character code to the buffer DATAOUT.
•Transfer of a character code to DATAOUT clears SOUT to 0.
•Initial state of SOUT is 1.
113

 Buffer registers DATAIN and DATAOUT, and status flags SIN

and SOUT are part of a circuitry known as device interface.

 To perform I/O transfers, we need machine instructions to:

 Monitor the status of the status registers.

 Transfer data among the I/O devices and the processor.

 Instructions have similar format to the instructions used for

moving data between the processor and the memory.
114

• How does the processor address the I/O devices?

– Some memory address values may be used to refer to

peripheral device buffer registers such as DATAIN and
DATAOUT.

– This arrangement is called as Memory-Mapped I/O.

– No special instructions are needed to access the contents of

the registers.
115

 Data can be transferred between these registers and the

processor using instructions such as Move, Load or Store.

 For example, contents of the keyboard character buffer

DATAIN can be transferred to register R1 in the processor by
the instruction

MoveByte DATAIN,R1
116

 The MoveByte operation code signifies that the operand size is

a byte.

 The Testbit instruction tests the state of one bit in the

destination, where the bit position to be tested is indicated by
the first operand.

Testbit #3,INSTATUS
117
 Stacks
118

 A stack is a special type of data structure where elements are

inserted from one end and elements are deleted from the same
end. This end is called the top of the stack.

 The various operations performed on stack:

1) Insert: An element is inserted from top end. Insertion

operation is called push operation.

2) Delete: An element is deleted from top end. Deletion

operation is called pop operation.
119

 A processor-register is used to keep track of the address of the

element of the stack that is at the top at any given time. This
register is called the Stack Pointer (SP).

 If we assume a byte-addressable memory with a 32-bit word

length,

1) The push operation can be implemented as

Subtract #4, SP

Move NEWITEM, (SP)

120

2) The pop operation can be implemented as

Move (SP), ITEM

Add #4, SP
121
 Suppose that a stack runs from location 2000 (BOTTOM) down no
further than location 1500.

122
 Suppose that a stack runs from location 2000 (BOTTOM) down no
further than location 1500.

123
 Queue
124

 Data are stored in and retrieved from a queue on a FIFO basis.

 Difference between stack and queue?

1) One end of the stack is fixed while the other end rises and
falls as data are pushed and popped.

2) In stack, a single pointer is needed to keep track of top of

the stack at any given time.
125

In queue, two pointers are needed to keep track of both

the front and end for removal and insertion respectively.

3) Without further control, a queue would continuously move

through the memory of a computer in the direction of higher
addresses. One way to limit the queue to a fixed region in
memory is to use a circular buffer.
 Subroutines
126

 A subtask consisting of a set of instructions which is executed

many times is called a Subroutine.

 A Call instruction causes a branch to the subroutine.

 At the end of the subroutine, a return instruction is executed.

 Program resumes execution at the instruction immediately

following the subroutine call.
127

 The way in which a computer makes it possible to call and

return from subroutines is referred to as its Subroutine Linkage
method.

 The simplest subroutine linkage method is to save the return-

address in a specific location, which may be a register
dedicated to this function. Such a register is called the Link
Register.
128

 When the subroutine completes its task, the Return instruction

returns to the calling-program by branching indirectly through
the link-register.

 The Call Instruction is a special branch instruction that

performs the following operations:

→ Store the contents of PC into link-register.

→ Branch to the target-address specified by the instruction.

129

• The Return Instruction is a special branch instruction that

performs the operation:

→ Branch to the address contained in the link-register.

130
 Subroutines
131

1. Subroutine Nesting And The Processor Stack

2. Parameter Passing

3. Stack Frame
 1. Subroutine Nesting And The Processor Stack
132

Subroutine Nesting means one subroutine calls another

subroutine.

 In this case, the return-address of the second call is also stored

in the link-register, destroying its previous contents.

 Hence, it is essential to save the contents of the link-register in

some other location before calling another subroutine.
Otherwise, the return-address of the first subroutine will be lost.
133

 Subroutine nesting can be carried out to any depth. Eventually,

the last subroutine called completes its computations and returns
to the subroutine that called it.

 The return-address needed for this first return is the last one
generated in the nested call sequence. That is, return-addresses
are generated and used in a LIFO order.

 This suggests that the return-addresses associated with

subroutine calls should be pushed onto a stack.
134

A particular register is designated as the SP(Stack Pointer) to

be used in this operation.

 SP is used to point to the processor-stack.

 Call instruction pushes the contents of the PC onto the

processor-stack.

 Return instruction pops the return-address from the processor-

stack into the PC.
 2. Parameter Passing
135

 The exchange of information between a calling-program and a

subroutine is referred to as Parameter Passing.
 The parameters may be placed in registers or in memory-
location, where they can be accessed by the subroutine.
 Alternatively, parameters may be placed on the processor-stack
used for saving the return-address.
 Following is a program for adding a list of numbers using
subroutine with the parameters passed through registers.
136
 3. Stack Frame
137

 Stack Frame refers to locations that constitute a private work-

space for the subroutine.

 The work-space is

→ created at the time the subroutine is entered &

→ freed up when the subroutine returns control to the calling-

program.
138
139

 Frame Pointer (FP) is used to access the parameters passed

→ to the subroutine &

→ to the local memory-variables.

 The contents of FP remains fixed throughout the execution of the

subroutine, unlike stack-pointer SP, which must always point to
the current top element in the stack.

 Operation on Stack Frame

 Initially SP is pointing to the address of oldTOS.

140

 The calling-program saves parameters on the stack.

 The Call instruction is now executed, pushing the return-address

onto the stack.

 Now, SP points to this return-address, and the first instruction of

the subroutine is executed.

 Now, FP is to be initialized and its old contents have to be

stored.
141

Hence, the first 2 instructions in the subroutine are:

Move FP,-(SP)

Move SP,FP

 The FP is initialized to the value of SP i.e. both FP and SP point

to the saved FP address.

 The local variables may now be pushed onto the stack. Space
for local variables is allocated by executing the instruction

Subtract #12,SP
142

 The subroutine now executes its task.

 When the task is completed, the subroutine pops the saved

values, removes the local variables from the stack frame by
executing the instruction.

Add #12, SP

 And subroutine pops saved old value of FP back into FP. At this
point, SP points to return-address, so the Return instruction can
be executed, transferring control back to the calling-program.
 Additional Instructions
143

1. Logic Instructions

2. Shift and Rotate Instructions

 Logical Shifts

 Arithmetic Shifts

 Rotate Operation

3. Multiplication and Division

 1. Logic Instructions
144

 Logic operations such as AND, OR, and NOT applied to

individual bits.
 These are the basic building blocks of digital-circuits.
 This is also useful to be able to perform logic operations in
software, which is done using instructions that apply these
operations to all bits of a word or byte independently and in
parallel.
 For example, the instruction
Not dst
 2. Shift and Rotate Instructions
145

 There are many applications that require the bits of an

operand to be shifted right or left some specified number of
bit positions.
 The details of how the shifts are performed depend on
whether the operand is a signed number or some more general
binary-coded information.
 For general operands, we use a logical shift.
 For a number, we use an arithmetic shift, which preserves the
sign of the number.
 Logical Shifts
146

 Shifting left (LShiftL) and Shifting right (LShiftR)

(a) Logical Shift left LShiftL #2,R0 (b)Logical Shift right LShiftR #2,R0
 Arithmetic Shifts
147
 Rotate Operation
148

#2,R0 #2,R0

#2,R0 #2,R0
 3. Multiplication and Division
149

 Some of the processor’s instruction sets supports Multiply and

Divide operations. For which they offer direct instructions to
multiply and/or divide on processor register operands.

 Multiply Ri, Rj
Rj ← [Ri] х [Rj]

 Divide Ri, Rj
Rj ← [Ri] / [Rj]
 Encoding of Machine Instructions
150

 To be executed in a processor, an instruction must be encoded

in a binary-pattern. Such encoded instructions are referred to
as Machine Instructions.

 The instructions that use symbolic-names and acronyms are

called assembly language instructions.

 We have seen instructions that perform operations such as add,

subtract, move, shift, rotate, and branch. These instructions may
use operands of different sizes, such as 32-bit and 8-bit
numbers.
151

 Let us examine some typical cases.

 The instruction

Add R1, R2

Has to specify the registers R1 and R2, in addition to the OP

code. If the processor has 16 registers, then four bits are
needed to identify each register. Additional bits are needed to
indicate that the Register addressing-mode is used for each
operand.
152

 The instruction

Move 24(R0), R5

Requires 16 bits to denote the OP code and the two registers,

and some bits to express that the source operand uses the
Index addressing mode and that the index value is 24.

 In all these examples, the instructions can be encoded in a 32-

bit word.
153
154

 The OP code for given instruction refers to type of operation

that is to be performed.

 Source and destination field refers to source and destination

operand respectively.

 The "Other info" field allows us to specify the additional

information that may be needed such as an index value or an
immediate operand.
155

 Using multiple words, we can implement complex

instructions, closely resembling operations in high- level
programming languages. The term complex instruction set
computers (CISC) refers to processors that use instruction sets of
this type.
 CISC approach results in instructions of variable length,
dependent on the number of operands and the type of
addressing modes used.
156

 In RISC (reduced instruction set computers), any instruction

occupies only one word.
 The RISC approach introduced other restrictions such as that all
manipulation of data must be done on operands that are
already in registers.
Add R1,R2,R3
 In RISC type machine, the memory references are limited to
only Load/Store operations.