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Basic Structure of
Computers
Computer Architecture
What is Computer Architecture?
• computer architecture is a set of rules and methods
that describe the functionality, organization, and
implementation of computer systems.
• Size
• Speed of operation
• Cost
• Computational power
• Type of application (Intended use)
PERSONAL COMPUTER (common form)
• homes, schools, and business offices
SUPER COMPUTERS
• Faster than mainframes
• Used for the large scale numerical calculations
• Applications are weather forecasting , aircraft design and
simulation
HANDHELD
• Also called a PDA (Personal
Digital Assistant).
• Typically used as an
appointment book, address
book, calculator, and notepad.
Calvin College
What is a computer?
• Simply put, a computer is a sophisticated electronic
calculating machine that:
– Accepts input information,
– Processes the information according to a list of internally stored
instructions and
– Produces the resulting output information.
• Functions performed by a computer are:
– Accepting information to be processed as input.
– Storing a list of instructions to process the information.
– Processing the information according to the list of instructions.
– Providing the results of the processing as output.
• What are the functional units of a computer?
13
1.2 FUNCTIONAL UNITS
• Input Unit
• Output Unit
• Memory Unit
Basic functional units of a
computer
Processor
Input
Control
Memory
ALU
Output
• NOTHING ELSE!
INPUT UNIT:
• accepts coded information and automatically converts the
external world data to a binary format, which can be transmitted
over a cable to either the memory or the processor
• Eg: Keyboard, Mouse, Joysticks, trackballs etc.
OUTPUT UNIT:
• Sends processed results to the outside world and converts the
binary format data to a format that a common man can understand
• Eg: Monitor, Printer, LCD, LED etc.
I/O UNIT:
• Performs both input and output functions
• Eg: Graphic displays
MEMORY UNIT:
• Store programs and data
•Two types of primary memory are RAM or R/W memory and ROM read
only memory
•ROM is used to store data and program which is not going to change.
• Instructions and data can be written into the memory or read out
under the control of the processor
• The control unit is the nerve center that sends control signals to
other units and sense their states
T1 Enable R1
T2 Enable R2
T4
•Control unit works with a
reference signal called
T1
processor clock
R1 R2
•Each basic step is
executed in one clock
cycle
R2
Basic Operational Concepts
Basic Function of Computer
• To Execute a given task as per the appropriate program
0 0 0 0th Location
0 0 1 1st Location
0 1 0
W/R
CS RD 0 1 1
A0 PROCESSOR
A1 1 0 0
A2
1 0 1
ADDRESS BUS
1 1 0
D7 D0
D0 D7
1 1 1
DATA BUS
Cont:-
last word
Example 2
A computer has 128 MB of memory. Each word in this computer
is eight bytes. How many bits are needed to address any single
word in memory?
Solution
The memory address space is 128 MB, which means 227.
However, each word is eight (23) bytes, which means that we
have 224 words. This means that we need log2 224, or 24 bits, to
address each word.
MEMORY OPERATIONS
• Today, general-purpose computers use a set of instructions called a
program to process data.
• 8000 54
• 8001 96
• 8002 78
• 8003
46
• 8004
|
Big Endian
• Big Endian (e.g., in IBM, Motorolla, Sun, HP)
» high order byte stored at lowest address
» byte3 byte2 byte1 byte0
0 0 1 2 3 0 3 2 1 0
4 4 5 6 7 4 7 6 5 4
• •
• •
• •
k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4
• R3 [R1] +[R2]
(2) Assembly Language Notation(ALN)
• RTN is easy to understand and but cannot be used to
represent machine instructions
• ALN is used to represent machine instructions and
programs
• Mnemonics (ALN) can be converted to machine
language, which is understandable by the processor
using assembler
Example:
1.MOVE LOC, R1 -> transfer from LOC to register R1
2.ADD R1, R2, R3 -> add R1 & R2 and place the sum in R3
Basic Instruction Types
C = A+B
• To execute this command, the contents of memory locations A and
B are fetched from memory and transferred into the processor. The
result is stored in location C.
[C] [A] + [B]
(1) Single machine instruction or Three-address instruction
• Add A,B,C
• Operands A and B are source operands and C is the destination
operand
• General format: Operation source 1, source 2, destination
• Advantage: Single instruction can perform the complete operation
• Disadvantage: Instruction code will be too large to fit in one word
location in memory
(2) Two-address instruction
• Add A,B
• [B] [A] + [B]
• Add A
• [AC] [AC] + [A]
• This instruction adds the content of memory location A to the
contents of accumulator and the result will be stored in
accumulator
• Load A – copies the contents of memory location A into
the accumulator
• Store A – copies the contents of the accumulator into memory
location A
• [C] [A] + [B] can be performed by executing the following
sequence of one-address instructions
Load A
Add B (accumulator is implied)
Store C
(4) Zero-address instruction
}
Begin execution here i Move A,R0
i+4 Add B,R0
3-instruction program
i+8 Move R0,C
. segment
.
.
A
.
.
.
C
• PC – Program counter: holds the address of the next
instruction to be executed
• Straight line sequencing: If fetching and executing of
instructions is carried out one by one from successive
addresses of memory, it is called straight line sequencing.
– B: 0 0 0 1 0 1 0 0 11011100
C=1 Z=0
S=1
V=0
Status Bits
Cn-1
A B
Cn ALU
F
V Z S C
Fn-1
Zero Check
Figure Format and different instruction types
Processing the instructions
Simple computer, like most computers, uses machine cycles.
During the execute phase, the instruction is executed and the results are
placed in the appropriate memory location or the register.
Once the third phase is completed, the control unit starts the cycle again,
but now the PC is pointing to the next instruction.
The process continues until the CPU reaches a HALT instruction.
Types of Addressing Modes
The different ways in which the location of the operand is
specified in an instruction are referred to as addressing
modes
• Immediate Addressing
• Direct Addressing
• Indirect Addressing
• Register Addressing
• Register Indirect Addressing
• Relative Addressing
• Indexed Addressing
Immediate Addressing
• Operand is given explicitly in the instruction
• Operand = Value
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
Instruction
opcode
operand
Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
Direct Addressing Diagram
Instruction
Opcode Address A
Memory
Operand
Indirect Addressing (1)
• Memory cell pointed to by address field
contains the address of (pointer to) the
operand
• EA = [A]
– Look in A, find address (A) and look there for
operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to
accumulator
Indirect Addressing (2)
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower
Indirect Addressing Diagram
Instruction
Opcode Address A
Memory
Pointer to operand
Operand
Register Addressing (1)
• Operand is held in register named in address
field
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
Register Addressing (2)
• No memory access
Operand
Register Indirect Addressing
• C.f. indirect addressing
• EA = [R]
• Operand is in memory cell pointed to by
contents of register R
• Large address space (2n)
• One fewer memory access than indirect
addressing
Register Indirect Addressing Diagram
Instruction
Opcode Register Address R
Memory
Registers
Registers
Mnemonics
Assembly Language
Assembler
Assembler Directives
• Assembly language is mostly a thin layer above the
machine structure.
• An assembly language is a low-level programming
language for a computer, microcontroller, or other
programmable device, in which each statement corresponds
to a single machine code instruction.
• Each assembly language is specific to a particular computer
architecture, in contrast to most high-level programming
languages, which are generally portable across multiple
systems.
• Assembly language is converted into executable machine
code by a utility program referred to as an assembler; the
conversion process is referred to as assembly, or assembling
the code.
• An assembler directive is a message to the assembler that tells the assembler
something it needs to know in order to carry out the assembly process;
for example, an assemble directive tells the assembler where a program is
to be located in memory.
• Examples of common assembler directives are ORG (origin), EQU (equate), and
DS.B (define space for a byte).
• Equate: The EQU assembler directive simply equates a symbolic name to a numeric
value.
Sunday EQU 1
Monday EQU 2
The assembler substitutes the equated value for the symbolic name; for
example, if you write the instruction ADD.B #Sunday,D2, the assembler treats it as if it
were ADD.B #1,D2.
Sunday EQU 1
(or)
Monday EQU Sunday + 1
In this case, the assembler evaluates "Sunday + 1" as 1 + 1 and assigns the
value 2 to the symbolic name "Monday".
ORG
sets the current origin to a new value. This is used to
set the program or register address during assembly.
For example, ORG 0100h tells the assembler to
assemble all subsequent code starting at address 0100h.
DS
Defines an amount of free space. No code is generated.
This is sometimes used for allocating variable space.
Basic Input/Output Operations
I/O
• The data on which the instructions operate are not
necessarily already stored in memory.
Main Cache
memory memory Processor
Bus
N S
T
R
How to improve T?
Pipeline and Superscalar Operation
• Instructions are not necessarily executed one after another.
• The value of S doesn’t have to be the number of clock cycles to
execute one instruction.
• Pipelining – overlapping the execution of successive
instructions.
• Pipelining is an implementation technique where multiple
instructions are overlapped in execution. The computer
pipeline is divided in stages. Each stage completes a part
of an instruction in parallel.
• Add R1, R2, R3
• Superscalar operation – multiple instruction pipelines are
implemented in the processor.
• Goal – reduce S (could become <1!)
Clock Rate
• Increase clock rate
Improve the integrated-circuit (IC) technology to make the
circuits faster
Reduce the amount of processing done in one basic step
(however, this may increase the number of basic steps
needed)
• Increases in R that are entirely caused by
improvements in IC technology affect all
aspects of the processor’s operation equally
except the time to access the main memory.
CISC and RISC
• Tradeoff between N and S
• A key consideration is the use of pipelining
S is close to 1 even though the number of basic steps per
instruction may be considerably larger
It is much easier to implement efficient pipelining in processor
with simple instruction sets
• Reduced Instruction Set Computers (RISC)
• Complex Instruction Set Computers (CISC)
Compiler
• A compiler translates a high-level language program into
a sequence of machine instructions.
• To reduce N, we need a suitable machine instruction set
and a compiler that makes good use of it.
• Goal – reduce N×S
• A compiler may not be designed for a specific processor;
however, a high-quality compiler is usually designed for,
and with, a specific processor.
Performance Measurement
• T is difficult to compute.
• Measure computer performance using benchmark programs.
• System Performance Evaluation Corporation (SPEC) selects and publishes
representative application programs for different application domains,
together with test results for many commercially available computers.
• Compile and run (no simulation)
• Reference computer
i 1
Multiprocessors and Multicomputers
• Multiprocessor computer
Execute a number of different application tasks in parallel
Execute subtasks of a single large task in parallel
All processors have access to all of the memory – shared-memory
multiprocessor
Cost – processors, memory units, complex interconnection networks
• Multicomputers
Each computer only have access to its own memory
Exchange message via a communication network – message-passing
multicomputers
UNIT IV
The Memory System
Control lines
( R / W , MFC, etc.)
Some basic concepts(Contd.,)
Measures for the speed of a memory:
memory access time.
memory cycle time.
An important design issue is to provide a
computer system with as large and fast a
memory as possible, within a given cost
target.
Several techniques to increase the effective
size and speed of the memory:
Cache memory (to increase the effective speed).
Virtual memory (to increase the effective size).
The Memory System
•
•
•
FF FF
A0 W1
•
•
•
A1
Address Memory
• • • • • • cells
decoder • • • • • •
A2
• • • • • •
A3
W15
•
•
•
T1 T2
X Y
Word line
Bit lines
Asynchronous DRAMs
• Static RAMs (SRAMs):
– Consist of circuits that are capable of retaining their state as long as the power
is applied.
– Volatile memories, because their contents are lost when power is interrupted.
– Access times of static RAMs are in the range of few nanoseconds.
– However, the cost is usually high.
CAS D7 D0
Fast Page Mode
Suppose if we want to access the consecutive bytes in
the selected row.
This can be done without having to reselect the row.
Add a latch at the output of the sense circuits in each row.
All the latches are loaded when the row is selected.
Different column addresses can be applied to select and place different bytes on
the data lines.
Consecutive sequence of column addresses can be
applied under the control signal CAS, without reselecting
the row.
Allows a block of data to be transferred at a much faster rate than random
accesses.
A small collection/group of bytes is usually referred to as a block.
This transfer capability is referred to as the
fast page mode feature.
Synchronous DRAMs
•Operation is directly synchronized
Refresh
counter with processor clock signal.
•The outputs of the sense circuits are
connected to a latch.
Row •During a Read operation, the
Row
address decoder Cell array contents of the cells in a row are
latch
Row/Column loaded onto the latches.
address •During a refresh operation, the
Column Column Read/Write contents of the cells are refreshed
address
counter decoder circuits & latches without changing the contents of
the latches.
•Data held in the latches correspond
Clock
to the selected columns are transferred
RA S to the output.
Mode register
CA S and Data input Data output •For a burst mode of operation,
register register
R/ W timing control successive columns are selected using
CS column address counter and clock.
CAS signal need not be generated
externally. A new data is placed during
Data
raising edge of the clock
Latency, Bandwidth, and DDRSDRAMs
• Memory latency is the time it takes to transfer
a word of data to or from memory
• Memory bandwidth is the number of bits or
bytes that can be transferred in one second.
• DDRSDRAMs
– Cell array is organized in two banks
Static memories
21-bit
addresses 19-bit internal chip address Implement a memory unit of 2M
A0
A1 words of 32 bits each.
Use 512x8 static memory chips.
A19 Each column consists of 4 chips.
A20
Each chip implements one byte
position.
A chip is selected by setting its
chip select control line to 1.
Selected chip places its data on the
2-bit
decoder data output line, outputs of other
chips are in high impedance state.
21 bits to address a 32-bit word.
High order 2 bits are needed to
512K 8
memory chip
D31-24 D23-16 D 15-8 D7-0
select the row, by activating the
four Chip Select signals.
512K 8 memory chip
19 bits are used to access specific
byte locations inside the selected
19-bit 8-bit data
address input/output chip.
Chip select
Dynamic memories
Large dynamic memory systems can be implemented
using DRAM chips in a similar way to static memory
systems.
Placing large memory systems directly on the
motherboard will occupy a large amount of space.
Also, this arrangement is inflexible since the memory system cannot be expanded easily.
Packaging considerations have led to the development
of larger memory units known as SIMMs (Single In-line
Memory Modules) and DIMMs (Dual In-line Memory
Modules).
Memory modules are an assembly of memory chips
on a small board that plugs vertically onto a single
socket on the motherboard.
Occupy less space on the motherboard.
Allows for easy expansion by replacement .
Memory controller
Recall that in a dynamic memory chip, to reduce the
number of pins, multiplexed addresses are used.
Address is divided into two parts:
High-order address bits select a row in the array.
They are provided first, and latched using RAS signal.
Low-order address bits select a column in the row.
They are provided later, and latched using CAS signal.
However, a processor issues all address bits at the same
time.
In order to achieve the multiplexing, memory
controller circuit is inserted between the processor
and memory.
Memory controller (contd..)
Row/Column
Address address
RAS
R/ W
CAS
Memory
Request controller R/ W
Processor Memory
CS
Clock
Clock
Data
152
The Memory System
Cache Memories
Cache Memories
Processor is much faster than the main memory.
As a result, the processor has to spend much of its time waiting while instructions
and data are being fetched from the main memory.
Major obstacle towards achieving good performance.
Speed of the main memory cannot be increased
beyond a certain point.
Cache memory is an architectural arrangement
which makes the main memory appear faster to
the processor than it really is.
The effectiveness of Cache mechanism is based
on the property of computer programs known as
“locality of reference”. Cache block –cache line
Locality of Reference
Analysis of programs indicates that many
instructions in localized areas of a program are
executed repeatedly during some period of time,
while the others are accessed relatively less
frequently.
These instructions may be the ones in a loop, nested loop or few procedures calling
each other repeatedly.
This is called “locality of reference”.
Temporal locality of reference:
Recently executed instruction is likely to be executed again very soon.
Spatial locality of reference:
Instructions with addresses close to a recently instruction are likely
to be executed soon.
Cache memories
Main
Processor Cache memory
• Write hit:
Cache has a replica of the contents of the main memory.
Contents of the cache and the main memory may be updated simultaneously.
This is the write-through protocol.
Update the contents of the cache, and mark it as updated by setting a bit
known as the dirty bit or modified bit. The contents of the main memory
are updated when this block is replaced. This is write-back or copy-back
protocol.
Cache miss
• If the data is not present in the cache, then a Read miss or Write miss occurs.
• Read miss:
Block of words containing this requested word is transferred from the memory.
After the block is transferred, the desired word is forwarded to the processor.
The desired word may also be forwarded to the processor as soon as it is transferred
without waiting for the entire block to be transferred. This is called load-through or
early-restart.
• Write-miss:
Write-through protocol is used, then the contents of the main memory are
updated directly.
If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word
is overwritten with new information.
Cache Coherence Problem
• A bit called as “valid bit” is provided for each block.
• If the block contains valid data, then the bit is set to 1, else it is 0.
• Valid bits are set to 0, when the power is just turned on.
• When a block is loaded into the cache for the first time, the valid bit is set to 1.
• Data transfers between main memory and disk occur directly bypassing the cache.
• When the data on a disk changes, the main memory block is also updated.
• However, if the data is also resident in the cache, then the valid bit is set to 0.
• What happens if the data in the disk and main memory changes and the write-
back protocol is being used?
• In this case, the data in the cache may also have changed and is indicated by the
dirty bit.
• The copies of the data in the cache, and the main memory are different. This is
called the cache coherence problem.
• One option is to force a write-back before the main memory is updated from the
disk.
Mapping functions
Mapping functions determine how memory
blocks are placed in the cache.
A simple processor example:
Cache consisting of 128 blocks of 16 words each.
Total size of cache is 2048 (2K) words.
Main memory is addressable by a 16-bit address.
Main memory has 64K words.
Main memory has 4K blocks of 16 words each.
Three mapping functions:
Direct mapping
Associative mapping
Set-associative mapping.
Direct mapping
Main
memory Block 0 •Block j of the main memory maps to j modulo 128 of
Block 1
the cache. 0 ,128,256..maps to block 0, 1,129,257 maps to
Cache
tag
Block1 and so on.
Block 0 •More than one memory block is mapped onto the same
tag position in the cache.
Block 1
•May lead to contention for cache blocks even if the
Block 127
cache is not full.
Block 128 •Resolve the contention by allowing new block to
tag
Block 127 Block 129
replace the old block, leading to a trivial replacement
algorithm.
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
Block 255 - When a new block is brought into the cache,
Tag Block Word
5 7 4 Block 256 then the next 7 bits determines cache position in which
this block must be stored.
Main memory address Block 257
- High order 5 bits determine which of the possible
32 blocks is currently present in the cache. These
are tag bits.
•Simple to implement but not very flexible.
Block 4095
Associative mapping
Main Block 0
memory
Block 1
•Main memory block can be placed into any cache
Cache
tag
position.
Block 0 •Memory address is divided into two fields:
tag
Block 1 - Low order 4 bits identify the word within a block.
- High order 12 bits or tag bits identify a memory
Block 127
block when it is resident in the cache.
Block 128 •Flexible, and uses cache space efficiently.
tag
Block 127 Block 129
•Replacement algorithms can be used to replace an
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Block 255
Tag Word
12 4 Block 256
Block 4095
Set-Associative mapping
Cache
Main Block 0 Blocks of cache are grouped into sets.
memory
tag Block 0 Mapping function allows a block of the main
Block 1
tag
memory to reside in any block of a specific set.
Block 1
Divide the cache into 64 sets, with two blocks per set.
tag Block 2 Memory block 0, 64, 128 etc. map to block 0, and they
tag Block 3 can occupy either of the two positions.
Block 63 Memory address is divided into three fields:
Block 64 - 6 bit field determines the set number.
tag - High order 6 bit fields are compared to the tag
Block 126 Block 65
fields of the two blocks in a set.
tag
Block 127 Set-associative mapping combination of direct and
associative mapping.
Number of blocks per set is a design parameter.
Tag Block Word
Block 127 - One extreme is to have all the blocks in one set,
Block 128 requiring no set bits (fully associative mapping).
6
6 4
- Other extreme is to have one block per set, is
Block 129
Main memory address the same as direct mapping.
Block 4095
The Memory System
Performance considerations
Performance considerations
• A key design objective of a computer system is to achieve the
best possible performance at the lowest possible cost.
– Price/performance ratio is a common measure of success.
• Performance of a processor depends on:
– How fast machine instructions can be brought into the processor for
execution.
– How fast the instructions can be executed.
Interleaving
Divides the memory system into a number of
memory modules. Each module has its own address buffer register
(ABR) and data buffer register (DBR).
Arranges addressing so that successive words in
the address space are placed in different
modules.
When requests for memory access involve
consecutive addresses, the access will be to
different modules.
Since parallel access to these modules is
possible, the average rate of fetching words from
the Main Memory can be increased.
Methods of address layouts
k bits m bits
mbits k bits
Module Address in module MM address
Address in module Module MM address
ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR
Virtual Memory
Virtual memories
Recall that an important challenge in the design
of a computer system is to provide a large, fast
memory system at an affordable cost.
Architectural solutions to increase the effective
speed and size of the memory system.
Cache memories were developed to increase the
effective speed of the memory system.
Virtual memory is an architectural solution to
increase the effective size of the memory system.
180
Virtual memories (contd..)
Recall that the addressable memory space depends on
the number of address bits in a computer.
For example, if a computer issues 32-bit addresses, the addressable memory space is 4G
bytes.
Physical main memory in a computer is generally not
as large as the entire possible addressable space.
Physical memory typically ranges from a few hundred megabytes to 1G bytes.
Large programs that cannot fit completely into the
main memory have their parts stored on secondary
storage devices such as magnetic disks.
Pieces of programs must be transferred to the main memory from secondary storage before
they can be executed.
181
Virtual memories (contd..)
When a new piece of a program is to be
transferred to the main memory, and the
main memory is full, then some other piece in
the main memory must be replaced.
Recall this is very similar to what we studied in case of cache memories.
Operating system automatically transfers data
between the main memory and secondary
storage.
Application programmer need not be concerned with this transfer.
Also, application programmer does not need to be aware of the limitations
imposed by the available physical memory.
182
Virtual memories (contd..)
Techniques that automatically move program and data
between main memory and secondary storage when they
are required for execution are called virtual-memory
techniques.
Programs and processors reference an instruction or data
independent of the size of the main memory.
Processor issues binary addresses for instructions and
data.
These binary addresses are called logical or virtual addresses.
Virtual addresses are translated into physical addresses by
a combination of hardware and software subsystems.
If virtual address refers to a part of the program that is currently in the main memory, it is accessed
immediately.
If the address refers to a part of the program that is not currently in the main memory, its contents
must be brought to the main memory before it can be used.
183
Virtual memory organization
Processor
•Memory management unit (MMU) translates
virtual addresses into physical addresses.
Virtual address
•If the desired data or instructions are in the
main memory they are fetched as described
Data MMU
previously.
•If the desired data or instructions are not in
Physical address
the main memory, they must be transferred
from secondary storage to the main memory.
Cache •MMU causes the operating system to bring
the data from the secondary storage into the
Data Physical address main memory.
Main memory
DMA transfer
Disk storage
184
Address translation
Assume that program and data are composed of
fixed-length units called pages.
A page consists of a block of words that occupy
contiguous locations in the main memory.
Page is a basic unit of information that is
transferred between secondary storage and main
memory.
Size of a page commonly ranges from 2K to 16K
bytes.
Pages should not be too small, because the access time of a secondary storage
device is much larger than the main memory.
Pages should not be too large, else a large portion of the page may not be used,
and it will occupy valuable space in the main memory.
185
Address translation (contd..)
• Concepts of virtual memory are similar to the
concepts of cache memory.
• Cache memory:
– Introduced to bridge the speed gap between the processor and the main
memory.
– Implemented in hardware.
• Virtual memory:
– Introduced to bridge the speed gap between the main memory and secondary
storage.
– Implemented in part by software.
186
Address translation (contd..)
Each virtual or logical address generated by a
processor is interpreted as a virtual page number
(high-order bits) plus an offset (low-order bits) that
specifies the location of a particular byte within that
page.
Information about the main memory location of each
page is kept in the page table.
Main memory address where the page is stored.
Current status of the page.
Area of the main memory that can hold a page is
called as page frame.
Starting address of the page table is kept in a page
table base register.
187
Address translation (contd..)
• Virtual page number generated by the
processor is added to the contents of the page
table base register.
– This provides the address of the corresponding entry in the page table.
188
Address translation (contd..)
PTBR holds Virtual address from processor
Page table base register
the address of
the page table. Page table address Virtual page number Offset
Virtual address is
interpreted as page
+ number and offset.
PAGE TABLE
PTBR + virtual
page number provide
the entry of the page This entry has the starting location
in the page table. of the page.
189
Address translation (contd..)
Page table entry for a page also includes some
control bits which describe the status of the page
while it is in the main memory.
One bit indicates the validity of the page.
Indicates whether the page is actually loaded into the main memory.
Allows the operating system to invalidate the page without actually removing it.
One bit indicates whether the page has been
modified during its residency in the main
memory.
This bit determines whether the page should be written back to the disk when it is
removed from the main memory.
Similar to the dirty or modified bit in case of cache memory.
190
Address translation (contd..)
• Other control bits for various other types of
restrictions that may be imposed.
– For example, a program may only have read permission for a page, but not
write or modify permissions.
191
Address translation (contd..)
Where should the page table be located?
Page table information is used by the MMU for every Read and Write access.
Ideal location for the page table is within the MMU.
Page table is quite large.
MMU is implemented as part of the processor
chip.
Impossible to include a complete page table on
the chip.
Page table is kept in the main memory.
A copy of a small portion of the page table can
be accommodated within the MMU.
This Portion consists of page table entries that correspond to the most recently
accessed pages.
192
Address translation (contd..)
A small cache called as Translation Lookaside
Buffer (TLB) is included in the MMU.
TLB holds page table entries of the most recently accessed pages.
Recall that cache memory holds most recently
accessed blocks from the main memory.
Operation of the TLB and page table in the main memory is similar to the operation
of the cache and main memory.
Page table entry for a page includes:
Address of the page frame where the page resides in the main memory.
Some control bits.
In addition to the above for each page, TLB must
hold the virtual page number for each page.
193
Address translation (contd..)
Virtual address from processor
194
Address translation (contd..)
How to keep the entries of the TLB coherent with
the contents of the page table in the main
memory?
Operating system may change the contents of
the page table in the main memory.
Simultaneously it must also invalidate the corresponding entries in the TLB.
A control bit is provided in the TLB to invalidate
an entry.
If an entry is invalidated, then the TLB gets the
information for that entry from the page table.
Follows the same process that it would follow if the entry is not found in the TLB or
if a “miss” occurs.
195
Address translation (contd..)
What happens if a program generates an
access to a page that is not in the main
memory?
In this case, a page fault is said to occur.
Whole page must be brought into the main memory from the disk, before
the execution can proceed.
Upon detecting a page fault by the MMU,
following actions occur:
MMU asks the operating system to intervene by raising an exception.
Processing of the active task which caused the page fault is interrupted.
Control is transferred to the operating system.
Operating system copies the requested page from secondary storage to
the main memory.
Once the page is copied, control is returned to the task which was
interrupted.
196
Address translation (contd..)
• Servicing of a page fault requires transferring
the requested page from secondary storage to
the main memory.
• This transfer may incur a long delay.
• While the page is being transferred the
operating system may:
– Suspend the execution of the task that caused the page fault.
– Begin execution of another task whose pages are in the main memory.
198
Address translation (contd..)
When a new page is to be brought into the main
memory from secondary storage, the main memory
may be full.
Some page from the main memory must be replaced with this new page.
How to choose which page to replace?
This is similar to the replacement that occurs when the cache is full.
The principle of locality of reference (?) can also be applied here.
A replacement strategy similar to LRU can be applied.
Since the size of the main memory is relatively larger
compared to cache, a relatively large amount of
programs and data can be held in the main memory.
Minimizes the frequency of transfers between secondary storage and main memory.
199
Address translation (contd..)
A page may be modified during its residency in
the main memory.
When should the page be written back to the
secondary storage?
Recall that we encountered a similar problem in
the context of cache and main memory:
Write-through protocol(?)
Write-back protocol(?)
Write-through protocol cannot be used, since it
will incur a long delay each time a small amount
of data is written to the disk.
200
The Memory System
Memory Management
Memory management
• Operating system is concerned with transferring programs and
data between secondary storage and main memory.
• Operating system needs memory routines in addition to the
other routines.
• Operating system routines are assembled into a virtual
address space called system space.
• System space is separate from the space in which user
application programs reside.
– This is user space.
• Virtual address space is divided into one
system space + several user spaces.
Memory management (contd..)
Recall that the Memory Management Unit (MMU) translates
logical or virtual addresses into physical addresses.
MMU uses the contents of the page table base register to
determine the address of the page table to be used in the
translation.
Changing the contents of the page table base register can enable us to
use a different page table, and switch from one space to another.
At any given time, the page table base register can point to
one page table.
Thus, only one page table can be used in the translation process at a
given time.
Pages belonging to only one space are accessible at any
given time.
Memory management (contd..)
When multiple, independent user programs coexist in the
main memory, how to ensure that one program does not
modify/destroy the contents of the other?
Processor usually has two states of operation:
Supervisor state.
User state.
Supervisor state:
Operating system routines are executed.
User state:
User programs are executed.
Certain privileged instructions cannot be executed in user state.
These privileged instructions include the ones which change page
table base register.
Prevents one user from accessing the space of other users.
The Memory System
Secondary Storage
Magnetic Hard Disks
Disk
Disk drive
Disk controller
Organization of Data on a Disk
Sector 0, track 1
Sector 3, trackn
Sector 0, track 0
System bus
Disk controller
Pit Land
Reflection Reflection
No reflection
0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0