B.

TECH PROJECT TITLE DEFEND SEMINAR 2019-20

National Institute of Science & Technology

Design of a Digital Filter

Project ID:17265

By
Abhishek Sahu Roll 201610389 (ECE)
Kunal Sunny Roll 201642242 (ECE)

Under the guidance of

Dr. Ajit Kumar Panda
ECE (201610389) & ECE (201642242) [1]
 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Content
National Institute of Science & Technology

 Aim/Objective of the Seminar

 Block Diagram

 Methodology

 Importance of the project

 Possible Outcomes

 Innovativeness

ECE (201610389) & ECE (201642242) [2]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Aim/Objective of the project

National Institute of Science & Technology

 The aim of this project is to design a Digital Filter (DSP system) that will
perform mathematical operation on a sampled, discrete-time signal to
reduce or enhance certain aspect of that signal.

 Digital filter goals is to reduce the complexity of Operation needed for

signal enhancing.

 It also aims in the three important design constraints like Area, delay
(performance) and power for designing this digital signal processing
system.

ECE (201610389) & ECE (201642242) [3]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Block Diagram
National Institute of Science & Technology

Filter Implementation

ECE (201610389) & ECE (201642242) [4]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Methodology
National Institute of Science & Technology

Design Specification,
Design Partition

Synthesize and Floor Planning ,

Design in Verilog
Gate-Level Netlist Power Planning

Simulation/Functional Generate Reports, Cell Placement

Verification Timing constraint file

Design Integration Post-Synthesis RC Extraction,

& Verification Design Validation GDSII

Digital Filter

ECE (201610389) & ECE (201642242) [5]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Methodology Contd.
National Institute of Science & Technology

 Designer must specify the functionality of the system. Basic blocks of

the hardware are identified and their interfaces, composed of data and
control signals, are fixed.

 After understanding the flow of all blocks, Next step is to implement

each block in MATLAB for Simulation Purpose.

 After each successful simulation we can implement whole blocks in

Hardware Description Language (HDL) Verilog and allowing functional
verification for each block.

 Filter will be designed based on Top to Bottom design flow using

CADENCE TOOL, cadence IC design environment. The design will be
based on the UMC 180nm technology process.

ECE (201610389) & ECE (201642242) [6]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Importance of the Project

National Institute of Science & Technology

 The techniques of DSP systems are extensively used in numerous

applications such as multimedia and communication.

 Recent trends in communication and mobile computing demand high

speed and ultra-low power DSP systems.

 Digital filters are useful for DSP applications like signal analysis. Hence
design of Digital filter is important factor.

ECE (201610389) & ECE (201642242) [7]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Possible Outcomes
National Institute of Science & Technology

 Design of digital filter will reduce the complexity of the operations of

filtering process.

 This filter design will be suitable for applications that require low power
consumption and high speed performance.

 The main advantage of the design will be it can be implemented in

which ever FPGA meaning that they are not dependent on the platform.

 It will add a different block by constituting to complete analogue to

digital converter (ADC).

ECE (201610389) & ECE (201642242) [8]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20

Innovativeness
National Institute of Science & Technology

 This project is different from others as this is going to be Implemented in

a software but We can see our product result in real time by using FPGA
platform.

 Functional Simulation will turn in to a part of IC Chip.

ECE (201610389) & ECE (201642242) [9]

 B.TECH PROJECT TITLE DEFEND SEMINAR 2019-20
National Institute of Science & Technology

THANK YOU!!

Presented By : Abhishek Sahu & Kunal Sunny [10]