Application of layers with internal stress

for silicon wafer shaping

J. Šik1, R. Lenhard1, D. Lysáček1, M. Lorenc1, V. Maršíková2, R. Hudec3,4

1ON Semiconductor Czech Republic
2Rigaku Innovative Technologies Europe
3Astronomical Institute of the Academy of Sciences of the Czech Republic
4Faculty of Electrical Engineering, Czech Technical University in Prague
1 Confidential Proprietary
 OUTLINE

• Theory

– Radius of curvature and warp

– Thin film stress

• Experiment

– LPCVD Poly-Si Films

– Squared wafer shape

• Multilayer stack design proposal

• Summary & Acknowledgements

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 RADIUS OF CURVATURE and WARP

What is the relation between R and w?

Assuming wafer shape is close to model.
D/2 WAFER

w  R  R cos( ) (1)
w
D

2R
D Wafer diameter
w Warp
R Radius of curvature

For small angle φ:

R
 2
cos( )  1 
2

Therefore, the Eq. (1) can be rewritten as

φ
2
D
w (2)
8R

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 RADIUS OF CURVATURE and WARP

1000,0

Radius of Curvature [m]

Wafer diameter
Wafer Warp [um] 100,0
diameter [mm] R = 10 m R=2m 100mm
150mm
100 120 630
200mm
150 280 1400 10,0

200 500 2500

1,0
10 100 1000
Warp [um]

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 ORIGIN of THIN FILM STRESS

• Thermal expansion

• Intrinsic
- growth
- misfit  tot   th   int   ext (3)
- phase transformation

• Extrinsic
- applied stress
- plastic deformation

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 THERMAL STRAIN and STRESS

Due to mismatch of thermal expansion coefficient between substrate (  s ) and film ( f ),

after temperature ramp down a strain (  th ) is built in.

DEPOSITION TEMPERATURE Tdep ROOM TEMPERATURE Troom

 f  s
Compressive stress in layer
THIN FILM

SUBSTRATE

 th  0  th  ( f   s )(Tdep  Troom )

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 THERMAL STRAIN and STRESS
Biaxial stress in thin film on thick substrate is related with strain:

E
 th   th (4)
1 

E Young’s modulus; Silicon (100) – 1.3·1011 N/m2

 Poisson’s ratio; Silicon (100) – 0.28

Material 
[1/°C]
Silicon 2,6·10-6
Polysilicon 2,8·10-6
Thermal SiO2 0,35·10-6
PECVD SiO2 2,3·10-6

LPCVD Si3N4 1,6·10-6

Aluminum 25·10-6
Tungsten 4,3·10-6

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 INTRINSIC THIN FILM STRESS

Thin film with residual stress  f on the COMPRESSIVE STRESS in layer

top of silicon wafer deform wafer THIN LAYER
according stress value and stress type
[S.Timoshenko, J. Opt. Soc. Am., 11, 233 (1925) ]
(compressive or tensile) w

E ts2 1 1 
f       (5) WAFER
6(1  ) t f  R R0 
E Young’s modulus ; Silicon (100) – 1.3·1011 N/m2 R
 Poisson’s ratio; Silicon (100) – 0.28
t s Wafer thickness
R Radius of curvature after film depo
R0 Radius of curvature before film depo
THIN LAYER
TENSILE STRESS in layer

Therefore the warp is proportional to the

residual stress and film thickness and
inversely proportional to the wafer
thickness squared. WAFER

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 THIN FILM STRESS VALUE

Example of residual stress in different depo and thermal growth layers are in tables.
Values are just indicative as the intrinsic stress may vary with the process conditions.

Compressive stress Tensile stress

Stress Stress
Layer Layer
[N/m2] [N/m2]

PECVD TEOS 1,8·108 APCVD SiO2 2,2·108

Thermal SiO2 3·108 LPCVD Si3N4 1·109

PECVD Si3N4 5·108

LPCVD Poly Si 2·108 *)

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 LPCVD Poly-Si FILMS
Heat treatment of poly-Si films can cause the atoms to move to low-energy positions. Poly-Si
thickness (THX) is proportional to the depo time, which can impact the stress in poly-Si films.

-50
[MPa]

-100
stress
Tensile Stress [MPa]

-150
Compressive

-200

-250

-300
600 700 800 900 1000 1100 1200 1300

Poly-Si THX [nm]

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 BACK SIDE LAYER
After depo of poly-Si (THX 1.5 m) and for wafer thickness 507 m the warp 110 m (R =
25.6 m) was achieved.

Wafer deformation map Warp profile perpendicular to

the facet

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 WAFER SHAPE
Circular 150 mm wafer, thickness 378 m, warp 181 m was squared to □ 100 mm.
Squared wafer keeps axially symmetrical shape.

160

140 4

120 4
3
2
100 2
Deviation (m)

1
80
1 3
60

40

20

0
-60 -40 -20 0 20 40 60
Position (mm)

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 WAFER SHAPE
Squared wafer has spherical shape. Deviation from ideal sphere is within 1 m.

180
measured data
160 spherical R=11.7m

140
deviation from sphere
1
120
Deviation (m)
Deviation (m)

100 0

80
-1

60
-60 -40 -20 0 20 40 60
Position (mm)
40

20

0
-60 -40 -20 0 20 40 60
Position (mm)

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 MULTILAYER STACK DESIGN

• To get low R we need to combine layers with high tensile stress on the front side and compressive
stress on the back side.
• All process steps have to keep high surface quality of the polished front side.

R < 10m

Layer with tensile stress

WAFER
THX ?

Layer with compressive stress

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 LAYER STACK AND WAFER THICKNESS

• For designed stack we can calculate the wafer thickness to achieve expected radius of curvature.
• As we can see in chart the wafer thickness 195 m would be needed for R ~ 2 m.
• That thin wafer is sensitive for handling and also it is affected by gravity sag.

7,0

6,0

5,0

4,0
R [m]

3,0

2,0

1,0

0,0
100 150 200 250 300 350 400
Wafer THX [um ]

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 SUMMARY & ACKNOWLEDGEMENTS
• Impact of thin film stress on wafer shaping has been reviewed.

• Layers with internal stress uniformly shape silicon wafer w/o deterioration of high quality of the
polished front side (surface RMS ~ 0.1 nm ).

• Stress in thin film is supposed to be constant regarding to the film thickness, which is valid for
most of dielectric thin films used in microelectronics, except of poly silicon.

• Stress in poly silicon layer is reduced with film thickness due to atoms migration into low
energy position.

• The circular wafer keeps the original axially symmetrical spherical shape after squaring. The
solid area can be build from squared segments.

• Multilayer stack has been designed to decrease the radius of wafer curvature to R ~ 2 m.

• For other than spherical shape photolithography has to be used. Suitable technology is
available in semiconductor industry.

• Research was partially supported by Projects MŠMT KONTAKT ME09028 & MŠMT ME0918.

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