Fixed Point Representations

FIXED POINT NUMBERS

Numbers: Fixed Point Numbers and Floating Point Numbers

Binary Fixed-Point Representation

X = xnxn-1xn-2 ... x1x0. x-1x-2 ... x-m
Sign Bit(xn): 0 for positive - 1 for negative
Remaining Bits(xn-1xn-2 ... x1x0. x-1x-2 ... x-m)
- Following 3 representations
Signed magnitude representation
Signed 1's complement representation
Signed 2's complement representation

Example: Represent +9 and -9 in 7 bit-binary number

Only one way to represent +9 ==> 0 001001
Three different ways to represent -9:
In signed-magnitude: 1 001001
In signed-1's complement: 1 110110
In signed-2's complement: 1 110111
In general, in computers, fixed point numbers are represented
either integer part only or fractional part only.
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 Fixed Point Representations

CHARACTERISTICS OF 3 DIFFERENT REPRESENTATIONS

Complement
Signed magnitude: Complement only the sign bit
Signed 1's complement: Complement all the bits including sign bit
Signed 2's complement: Take the 2's complement of the number,
including its sign bit.

Maximum and Minimum Representable Numbers and Representation of Zero

X = xn xn-1 ... x0 . x-1 ... x-m

Signed Magnitude
Max: 011 ... 11.11 ... 1
Min: 111 ... 11.11 ... 1
Zero: +0 000 ... 00.00 ... 0
-0 100 ... 00.00 ... 0

Signed 1’s Complement Signed 2’s Complement

Max: 011 ... 11.11 ... 1 Max: 011 ... 11.11 ... 1
Min: 100 ... 00.00 ... 0 Min: 100 ... 00.00 ... 0
Zero: +0 000 ... 00.00 ... 0 Zero: 0 000 ... 00.00 ... 0
-0 111 ... 11.11 ... 1

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 Fixed Point Representations

ARITHMETIC ADDITION: SIGNED MAGNITUDE

[1] Compare their signs
[2] If two signs are the same ,
ADD the two magnitudes - Look out for an overflow
[3] If not the same , compare the relative magnitudes of the numbers and
then SUBTRACT the smaller from the larger --> need a subtractor to add
[4] Determine the sign of the result

6+9 -6 + 9
6 0110 9 1001
+) 9 1001 -)6 0110
15 1111 -> 01111 3 0011 -> 00011

6 + (- 9) -6 + (-9)
9 1001 6 0110
-) 6 0110 +) 9 1001
- 3 0011 -> 10011 -15 1111 -> 11111
Overflow 9 + 9 or (-9) + (-9)
9 1001
+) 9 1001
overflow (1)0010
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 Fixed Point Representations

ARITHMETIC ADDITION: SIGNED 2’s COMPLEMENT

Add the two numbers, including their sign bit, and discard any carry out of
leftmost (sign) bit

Example
6 0 0110 -6 1 1010
+) 9 0 1001 +) 9 0 1001
15 0 1111 3 0 0011

6 0 0110 -9 1 0111
+) -9 1 0111 +) -9 1 0111
-3 1 1101 -18 (1)0 1110

9 0 1001 overflow
+) 9 0 1001
18 1 0010 2 operands have the same sign
and the result sign changes

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 Fixed Point Representations

ARITHMETIC ADDITION: SIGNED 1’s COMPLEMENT

Add the two numbers, including their sign bits.

- If there is a carry out of the most significant (sign) bit, the result is
incremented by 1 and the carry is discarded.

Example end-around carry

6 0 0110 -6 1 1001
+) -9 1 0110 +) 9 0 1001
-3 1 1100 (1) 0(1)0010
+) 1
3 0 0011
not overflow

-9 1 0110 9 0 1001
+) -9 1 0110 +) 9 0 1001
(1)0 1100 1 (1)0010
+) 1
0 1101
overflow
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 Fixed Point Representations

COMPARISON OF REPRESENTATIONS

* Easiness of negative conversion

S + M > 1’s Complement > 2’s Complement

* Hardware

- S+M: Needs an adder and a subtractor for Addition

- 1’s and 2’s Complement: Need only an adder

* Speed of Arithmetic

2’s Complement > 1’s Complement(end-around C)

* Recognition of Zero

2’s Complement is fast

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 Addition and Subtraction

4-bit BINARY ADDER

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 Addition and Subtraction

4-bit BINARY ADDER-SUBTRACTOR

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 Addition and Subtraction

SIGNED MAGNITUDE ADDITION AND SUBTRACTION

Addition: A + B ; A: Augend; B: Addend

Subtraction: A - B: A: Minuend; B: Subtrahend
Add Subtract Magnitude
Operation Magnitude When A>B When A<B When A=B
(+A) + (+B) +(A + B)
(+A) + (- B) +(A - B) - (B - A) +(A - B)
(- A) + (+B) - (A - B) +(B - A) +(A - B)
(- A) + (- B) - (A + B)
(+A) - (+B) +(A - B) - (B - A) +(A - B)
(+A) - (- B) +(A + B)
(- A) - (+B) - (A + B)
(- A) - (- B) - (A - B) +(B - A) +(A - B)

Hardware Implementation Bs B Register

AVF Complementer M(Mode Control)

E Output Input
Parallel Adder
Carry Carry
S
As A Register Load Sum
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 SIGNED MAGNITUDE ADDITION AND SUBTRACTION
• A and B are registers, As and Bs are FFs to store sign bit.
• The output carry is transferred to the E FF.
• AVF(Add oVerflow FF): hold overflow bit when A and B are added
• When M=0, it act as a adder
• When M = 1, it act as subtractor
• The two signs As and Bs are compared by an XOR-gate.
• If the output of the gate is:
– 0, the sign are identical
– 1, the sign are different
• For an add operation, identical signs dictate that the magnitudes be added
• For a subtract operation, difference signs dictate that the magnitudes be
added.
• The magnitudes are added with micro-operation :
EAA+B
• For an add operation, different signs dictate that the magnitudes be
subtracted.
• For a subtract operation, identical signs dictate that the magnitudes be
subtracted.

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11
 SIGNED MAGNITUDE ADDITION AND SUBTRACTION
• The carry in E after the addition constitute an overflow if E=1.
• The value of E is transfer into the AVF.
• No overflow if the numbers are subtracted so AVF is cleared to ‘0’.
• E=1 indicates that A>=B and the number in A is correct result. If A is ‘0’ then
the sign As bit must be made positive to avoid negative ‘0’.
• E=0, indicates that A<B, so it is necessary to take 2’s complement of the
value in A.
• When A<B the sign bit of the result is the complement of the original sign of
A.
• Final result is found in register A and it’s sign in A.

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 Addition and Subtraction

SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION

• The leftmost bit of binary number represents the sign bit: ‘0’ for (+ve) and
‘1’ for (-ve).
• If sign bit is 1, the entire number is represented in 2’s complement form.
• Addition:
– Sign bits treated same as the other bits of the number.
– A carry out of the sign bit position is discarded.
• Subtraction:
– Taking 2’s complement of subtrahend.
– Then adding it to the minuend.
• Overflow occurred when two numbers are added and sum occupies n+1
digits.
• An overflow can be detected by inspecting the last two carries out of the
addition.
• Cin and Cout of most significant bit are applied to the X-OR gate,
• Overflow detected when Cin X-OR Cout = 1
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 Addition and Subtraction

SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION

Register configuration for hardware implementation
• This is the same configuration as previous except that sign bits are not
separated from rest of the bits.
• Considered A as AC register and B as BR register.
• Leftmost bit in AC and BR are represents sign bits of numbers.
• The two sign bits are added or subtracted together with the other bits in
the complementer and parallel adder.
• The overflow bit V is set to 1 if x-or of last two carries is 1, and it is cleared
otherwise.
Hardware
B Register

V Complementer and
Parallel Adder
Overflow

AC

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 SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION
Hardware implementation algorithm
• Addition: Sum is obtained by adding the contents of registers AC and BR.
Overflow should be obtained by observing the flip-flop V.
• Subtraction:
– The subtraction operation is accomplished by adding the contents of AC to 2’s complement
of BR.
– Taking 2’s complement of BR has effect of changing a (+ve) number to (-ve), and vice versa.
– An overflow must be checked during this operation because the two numbers added could
have the same sign.
Flowchart
Subtract Add

Minuend in AC Augend in AC
Subtrahend in B Addend in B

AC  AC + B’+ 1 AC  AC + B
V  overflow V  overflow

END END 15
 Ranges
Binary
No. of Unsigned Sign-magnitude 2’s complement
bits Min Max Min Max Min Max
1 0 1
2 0 3 -1 1 -2 1
3 0 7 -3 3 -4 3
4 0 15 -7 7 -8 7
5 0 31 -15 15 -16 15
6 0 63 -31 31 -32 31
Etc.

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 In General
Binary
No. of Unsigned Sign-magnitude 2’s complement
bits
Min Max Min Max Min Max

n n-1 n-1 n-1 n-1

n 0 2 - 1 -(2 - 1) 2 -1 -2 2 -1

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 Multiplication

MULTIPLICATION

Multiplication: B * A; B: Multiplicand; A: Multiplier; P: Partial Product

Multiplication of Unsigned Positive Numbers

A = An-1An-2 ... A0
B = Bn-1Bn-2 ... B0

P=B*A
n-1
= B * (  2i * Ai )
i=0
= An-1 * (B2n-1) + An-2 * (B2n-2) + ... + A0 * (B20)
B shifted left B shifted left B shifted left
n-1 bits n-2 bits 0 bits = A
Or
B shifted (n-1) bits to the left

P = An-1*(B2n-1 * 20) + An-2*(B2n-1 * 2-1) + ... + A0*(B2n-1 * 2-(n-1))

B2n-1 B2n-1 shifted right B2n-1 shifted right

1 bit (n-1) bits

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 Multiplication

MULTIPLICATION

Multiplication of Unsigned Binary Integers

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 Multiplication

MULTIPLICATION
Multiplication of signed magnitude data
• The multiplier and multiplicand are loaded into two registers (B and Q).
• A third register, the A register, is also needed and is initially set to 0.
• There is also a 1-bit E register, initialized to 0, which holds a potential carry
bit resulting from addition.
• Flip-flops As , Bs, and Qs are used to store the sign bit.
• A sequence counter is used to store the number of bits in multiplier.
• The operation of the multiplier is as follows:
– Control logic reads the bits of the multiplier one at a time.
– If Qn is 1, then
1. The multiplicand is added to the A register and the result is stored in the A register,
with the E bit used for overflow.
2. All of the bits of the E, A, and Q registers are shifted to the right one bit, so that the E
bit goes into An-1, A0 goes into Qn-1 and Qn is lost.
– If Qn is 0, then no addition is performed, just the shift.
– This process is repeated until SQ=0.
• Final result is obtained in EAQ registers.
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 Multiplication

Multiplication of signed magnitude data

Hardware

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Algorithm Multiplication

SIGNED MAGNITUDE MULTIPLICATION

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 Multiplication

EXAMPLE

Numerical Example
23 X 19 = 10111 X 10011

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 Multiplication

BOOTH MULTIPLICATION ALGORITHM FOR SIGNED 2’S COMPLEMENT

Multiplier
Strings of 0’s: No addition; Simply shifts
Strings of 1’s: String of 1’s from mp to mq: 2p+1 - 2q

Example
001110 (14) -> p = 3, q = 1
001110 = 23+1 - 21

M * 14 = M24 - M21

Algorithm
[1] Subtract multiplicand for the first least significant 1 in a string of
1’s in the multiplier.
[2] Add multiplicand for the first 0 after the string of 1’s in the
multiplier.
[3] Partial Product does not change when the multiplier bit is identical
to the previous bit.

110010 = -24 + 22 - 21 = -16 + 4 - 2 = -14

subtract Add subtract

24 22 21
HARDWARE FOR BOOTH MULTIPLICATION ALGORITHM

Arithmetic Shift Right

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BOOTH ALGORITHM FOR SIGNED 2’S COMPLEMENT

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 EXAMPLE OF BOOTH MULTIPLIER
Example:
for n = 5
-9 X -13 =117

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 DIVISION ALGORITHM

Example of binary division

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 Division Algorithm
Division of signed magnitude data
• Divisor is stored in register B and double length dividend is stored in
register A and Q.
• The dividend is shifted to the left and the divisor is subtracted by adding it
2’s complement value.
• If E=1, it signifies that A>=B, then
– A quotient bit 1 is inserted into Qn.
– and partial remainder is shifted to the left to repeat the process.
• If E=0, it signifies that A<B, then
– Quotient Qn remains 0 (inserted during the shift).
– The value of B is then added to restore the partial remainder in A to its previous value.
• The partial remainder is shifted to the left and the process is repeated
again until all the quotient bits are formed.
• Register EAQ is now shifted to the left with 0 inserted into the Qn and
previous value of E is lost.

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 Division Algorithm
Sign of the result
• The sign of the quotient is determined from the signs of the dividend and
the divisor.
– If the signs of the dividend and the divisor are alike the sign of quotient is (+).
– If the signs of the dividend and the divisor are unlike the sign of quotient is (-).

Divide Overflow
• When the dividend is twice as long as divisor, the condition for overflow
can be stated as follows:
• Divide overflow is detected by a divide overflow flip-flop DVF
– The divide overflow occur if the higher order bits of dividend constitute a number
greater then or equal to the divisor.

Divide by zero problem

• The overflow conditions take care of this condition as well.
• This occurs when dividend will be greater than or equal to a divisor which
is equal to zero.
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 Division Algorithm
Hardware
• The dividend is in A and Q and the divisor is in B.
• The sign of the result is transferred into Qs to be a part of quotient.

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A / B = Q + R , A: Dividend; B: Divisor; Q: Quotient; R: Remainder

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Divisor B = 10001, B’+ 1 = 01111

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