SPI(Serial Peripheral Interface Bus)

SPI is a synchronous serial protocol proposed by Motorola to be used as standard

for interfacing peripheral chips to a microcontroller.

The SPI protocol uses four wires to carry out the task of data communication:
SPI requires two control lines (CS and SCK) and two data lines (SDI and SDO)
Devices are classified into the master or slaves.

SPI data transfer is initiated by the master device. A master is responsible for
generating the SCK signal to synchronize the data transfer.

The SPI protocol is mainly used to interface with shift registers, LED/LCD
drivers, phase locked loop chips, memory components with SPI interface, or A/D or
D/A converter chips.
With CS active low, the corresponding peripheral device is selected. A master, usually the
host micro controller, always provides clock signal to all devices on a bus whether it is
selected or not. Only one master must be active on a bus at a time. The SPI protocol
operates in full duplex mode, when input and output data transfers on both lines
simultaneously. The unselected devices keep the SDO lines in hi-Z state and therefore
inactive.
Since the clock serves as synchronization of the data communication, there are four
possible modes that can be used in an SPI protocol, based on clock polarity (CPOL) and
clock phase (CPHA) as shown in Table 1 and Figure 2.
If the phase of the clock is zero (i.e. CPHA = 0) data is latched at the rising edge of the clock
with CPOL = 0, and at the falling edge of the clock with CPOL = 1. If CPHA = 1, the
polarities are reversed. Data is latched at the falling edge of the clock with CPOL = 0, and at
the rising edge with CPOL = 1. All Intersil’s SPI DCPs support Mode 0 (CPOL = 0,
CPHA = 0) protocol.
For this mode, input data (SDI) is latched in by the low-to-high transition of clock
SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL
 Read and write cycles
Address and data are shifted MSB first into the serial data input (SDI) and out of
the serial data output (SDO).
Any data transfer considers the first bit to define whether a READ or WRITE will
occur. This is followed by seven bits defining the address to be read or written.
Data is transferred out of the SDO for a READ operation and into the SDI for a
WRITE operation.
The address is always the second through the eighth bit written after the enable
(E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is
a '0,' one or more READ cycles will occur
Read mode sequence
Write mode sequence
In SPI, a master can communicate with a single or multiple slaves. In the case of a single
slave, the slave-select signal can be tied to the local ground potential of the slave device
to allow for permanent access. For applications using multiple slaves, two
configurations are possible: independent and daisy-chained slaves
Addressing slaves independently, the master must provide multiple slave-select signals.
This configuration is often used in data acquisition systems where multiple ADCs and
DACs must be accessed individually. Daisy-chained slaves require the master to provide
only one slave-select signal as this configuration demands all slaves to be enabled at the
same time to ensure an uninterrupted flow of data through all shift registers within the
chain. Typical applications are cascaded, multi-channel input serializes and output
drivers in industrial I/O modules.