TX-LEVEL EXTRACTION FLOW -

STARLITE
TOPICS
 What is StarLite?

 Why use StarLite ?

 Tx-Level Extraction Flow

 Tasks done in Development

What is StarLite?
A utility meant for automation of the various steps involved in
Transistor- level extraction flow.

Automates eda tool invocation.

Carries out data pre-processing and post-processing and data collection

from pdk.

Includes a GUI as well as command line interface.

What is StarLite? (Cont’d)
StarLite comprises of following 8 steps:

1. Pre-process
-Instance/net name collision check
-Net/tie file error check

2. Globalwire
-NOTE: Not supported by all PDKs.
-Creates a gdsII containing either metal tracks or metal plates on
the specified layers. This gdsII is used to artificially increase the
capacitance on the shapes in the existing design in an attempt
to mimic how the cell will behave once it’s been placed.

3. Stress
-Runs stress effect calculation code which generates a file
containing the stress parameters for each device.
What is StarLite? (Cont’d)
4. LVS (Layout Versus Schematic)
-Runs Mentor’s Calibre tool
-Identifies which shapes in the GDSII file correspond to which
nets/instances in the schematic (CDL/spice) netlist.

5. Query
-Runs Mentor’s Calibre tool
-Generates a number of files, including an annotated GDSII and an
ideal layout spice netlist, which are used as input to the LPE
(Layout Parasitic Extraction) tool.

6. Post-query
-If the LPE tool is Star-RCXT, then it modifies the output of the
Query stage so Star-RCXT will place the gate node at the center of
the mosfet instead of at one of the ends (the orientation of the
transistor determined which end the node would appear on).
What is StarLite? (Cont’d)
7. LPE (Layout Parasitic Extraction)
-Uses Cadence’s QRC tool
-Cadence’s Assura RCX and Synopsys’ Star-RCXT tools are also
supported for legacy PDKs.
-Performs transistor-level extraction using the output from the
Query (and Post-query) stages.
8. Post-process
-NOTE: This stage is not run if netlist format is dfII.
-Fixes the formatting of the extracted DSPF or spice netlist for
use with various simulators and analysis tools.
-If only extracting a subset of nets, then automatically ties off
non-extracted nets.
-If pwrGnd simple is selected, then it prunes down the pwr/gnd
nets.
-Additionally, it corrects the terminal order of devices to match
the schematic, and back annotates the netlist to use schematic
instance/net names.
Why use StarLite?