Scaling

S. C. Bose
scbose@iitj.ac.in
 VLSI has been an area of rapid and relentless technological
development – technological obsolescence
Moore’s Law (in 1965): transistor density of integrated circuits doubles
every two years. 1980 – every 18 months

The feature size has reduced from 10µm to 0.09 µm (next generation) through
sequence of 6, 5, 3, 2, 1.5, 1.0, 0.8, 0.6, 0.5, 0.35, 0.25, 0.18, 0.15, 0.13.
The silicon wafer size has gone from 2 inches to 12 inches through 3, 4, 5, 6, 8.
Chip size has increased from 2 by 2 mm to 2 by 2 cm.

Typically after every 3 or 4 generations of technological change, the silicon

wafer size changes. This and the feature size requirement of the next generation
technology necessitate a complete revamping of the production plant
environment and its machinery. Thus, the production plant may have an
economically useful life of only 7 to 8 years.

The next generation plant and machinery is around a factor of 4 to 5 times more
expensive than the previous generation.
 So one needs a ready portfolio of products and technology(ies) to quickly ramp up
the production of the new plant to its full capacity – to make its operation
economically viable and to earn sufficient so as to invest in the next generation
technology before the obsolescence sets in.

While plant & machinery have become more expensive with every new generation
of technology, the cost of transistor unit that they produce is steadily declining.

More complex next generation products are typically cheaper than the less complex
older generation products, hence product obsolescence. One transistor used to
cost $6 in 1965, in 1999 16Mbit DRAM cost $6.
A judicious combination of structural parameters and operating voltages of transistor
with small feature sizes permits these transistors to operate faster and consume less
power. Hence, besides cost advantages, there is both speed and power benefits offered
by next generation technology.

Computing ability has been enhanced 2 million times. Clock rate 0.5 Mhz 2 GHz
(4000 times), word length 4 bits 64 bits (16 times), 8 cycle ¼ cycle (32 times).
4000  16  32  2  10 6
John Kilby commercialised the MOS based Integrated
Circuits in 1959.

Boolean Algebra led to the concept of digital logic.

There are eight major families of logic :

Register-Transistor Logic (RTL), Diode-transistor logic (DTL),

Transistor-transistor logic (TTL), Complementary transistor logic
(CTL), Emitter-coupled logic (ECL), Metal Oxide Semiconductor
(MOS) logic, Complementary Metal-Oxide Semiconductor
(CMOS) and Integrated Injection Logic (IIL)

MOS or planar technology became commercially viable and

CMOS is most popularly used from low power point of view.
The Moore’s law which is still valid has ensured that supply of
transistors on the chip continuously exceeds their need visualized by
the product designer.

The real challenge lies in the ability to quickly and correctly design
complex chips.

The productivity growth in ICs is possible through design innovation, device

miniaturisation, wafer size increase, yield improvements and improvements in
equipment utilisation.

Decreasing device dimensions (feature size) contributes maximum to the

productivity growth in ICs.
 MOS Transistor

•MOS Transistor (MOSFET) is a four terminal device. The four terminals are
Source (S), Drain (D), Gate (G) and Bulk (B).
•The source and drain terminals are symmetrical; electrical voltages applied to
them determine which terminal act as source and drain.
•Gate to Source voltage (Vgs) and to a lesser extent Bulk to source voltage
(Vbs) determine whether or not a conducting surface-channel (channel) exists
between the drain and source.

No DC current can flow through the gate terminal (as well as the
bulk terminal which is also isolated by the insulating depletion
layer from the channel, source and drain regions).
 W
G
t ox
N D Xj S
L D Xj N D

Substrate (P-Type)
 Short Channel Effects

Only lateral shrinkage of device dimensions (L & W) distorts

electrical behaviour (I  V) of the transistor. This may result in
undesirable short channel effects.
Short channel effects are:
•Dependence of Vt on L, W and biasing voltages
•Degradation of subthreshold behaviour
•Failure of saturation current through punch through
•Oxide charging and Vt shift
•Device cannot be turned off properly
 Time Constant

•: the fundamental time constant of a MOS technology

(Process).
•Transit time: Circuit delays in MOS transistor circuits are
caused by charging and discharging of the transistor gate
capacitances through the channel of another MOSFET.
•The charging time of the gate capacitance of the smallest
possible MOSFET by the ‘ON’ resistance (RON) of another
similar transistor therefore is a fundamental time constant and is
the basic measure of the circuit speed. It is typically called .

L2 Cg
  RON C g 
 (Vgs  Vt )
Vds L2
R ON  
I ds μCox (Vg  Vt )
 Miniaturisation

Miniaturised circuit would dissipate too much power and heat

generated would be too much for the underlying silicon to
conduct away.
Thus, for miniaturising the device without running into any of
the above mentioned problems (retaining long channel
behaviour), device dimensions, structural parameters and
voltages need to be changed in coordinated manner so that
•Electrical characteristics of the device do not deteriorate.
•Circuits occupy smaller area.
•Circuit speed increases.
•Circuit power consumption/unit area even at increased
speed does not exceed the heat removal ability of silicon.
Scaling principles were first formulated by Richard Dennard in
1974. Different scaling principles have been formulated and are
listed as follows:

parameter CE QCV CV CD QCD1 QCD2

voltages k-1 k-1/2 1 k-1 k-1 k-1
L&W k-1 k-1 k-1 1 1 k-1/2
tox k-1 k-1 k-1/2 1 k-1/2 k-1/2
Sub. Dop k k k 1 1 k-1/2

•The CE principle improves circuit performance by reducing

voltage swing and capacitances while it ensures reliability by
keeping the electric field constant. Thickness of the interconnect
line is not scaled down, hence performance is not as expected.
•Considering noise margin, voltage is not scaled down in CV
scaling. 5 volt supply standard is maintained for several steps of
shrinkage in L & W. This is used for TTL compatibility.
However, because of higher field, reliability is not very good and
this is not used for low voltage and low power application.
•QCV provides optimum drive capability in digital circuits. It
also provides best overall analog performance with increase in
unity gain bandwidth and moderate degradation of gain and
SNR.
•CD, QCD1 and QCD2 are for low voltage circuits.
This results in scaling down of the electrical parameters, circuit
power, circuit power density, device current and  (hence clock
frequency) etc.
Parameter Symbol CE CV
Current I k-1 k½
Total gate Cg k-1 k-3/2
capacitance
Oxide Cox k k½
capacitance
Threshold Vt k-1 1~-
Delay time =VC/I k-1 k-2
Circuit power VI k-2 k½
Power density VI/A 1-- k5/2
Scaling is defined as coordinated change in geometrical and structural parameter
of MOSFET so that less silicon area is occupied by the device while retaining
appropriate electrical behaviour.
Initially two types of scaling : Constant Field Scaling and Constant Voltage
Scaling were proposed.

parameter CE QCV CV CD QCD1 QCD2 CE reduces voltage,

voltages k-1 k-1/2 1 k-1 k-1 k-1 capacitances, field is const.
Interconnect line is not
L&W k-1 k-1 k-1 1 1 k-1/2 scaled. CV is for TTL
tox k-1 k-1 k-1/2 1 k-1/2 k-1/2 compatibility not for low
Sub. Dop k k k 1 1 k-1/2 power
CD scaling gives
gd 1 k3/4 k k-3/2 k-1 k-3/4 performance degradation in
vnT/f½ 1 k-1/4 k-1/4 k1/2 k1/4 K1/4 thermal noise, delay, I, gm.
Results in lowest power
Delay k-1 k-3/2 k-2 k k 1
density, power dissipation
P k-2 k-1/2 k1/2 k-3 k-5/2 k-5/2 and improved drain
P/A 1 k3/2 k5/2 k-3 k-5/2 k-3/2 conductance (gd).
 Vt in does not obey scaling principles properly.
Below Vt conductance is not strictly zero.
1/ 2 1
( V g s Vt )
R
1 KT

e q

R
0.2 1
V V
0.5 volt ( 20 KT/q) below Vt device 1 is off because conductance is
decreased by 107 times.
For device 2 conductance decreases by 102 times.
Temperature is not a scaling parameter.

Power density increases in CVS, so new type of packaging other than ceramic
and plastic should be tried.
The relationship between minimum channel length and other
structural parameters

Lmin  0.4X jtox (Ws  WD ) 

1
 0.4
2 3 1
3

Long Channel a MOS transistor is called a

Lmin short-channel device if its
channel
Short Channel length is of the same order of
magnitude as the depletion
region thicknesses of the
 source
and drain junctions.
 Interconnect Layer Scaling
 Lk
•Line resistance R´ = t k W k  kR
•Line capacitance C´=
 L W
d k k k  C
k

•Line response time (RC) remains the same.

I
•Voltage drop along line V´d = k (kR)
For constant chip size, the length of a signal path that traverses
I
k

the chip does not scale down.

R'  k 2 R V'd  kVd  '  kRC  k

This inhibits to take full advantage of higher switching speed

inherent in the scaled down devices when signals are required to
propagate over long path.
Therefore, organisation of the distribution of clock signals
should be done carefully while scaling down the circuits.

Average gate delay is determined by the interconnection rather

than the gate itself.

Wire delays become dominant because of their non-scaling

nature vis-à-vis gate delays which scale down.

Line current density increases by factor k and this may lead to

metal migration. So new type of metallization and reduction in
the system current are required.
Aggressive scaling of CMOS devices in each technology
generation has resulted in higher integration density and
performance.
Five orders of magnitude in processor performance (in
MIPS) has been achieved.

Moore’s law will be around for some more time.

TIPS is expected. For this to happen, frequency of transistor
operation should also increase as the integration so that more
complex system can be realised. For this, supply voltage
should also be reduced and hence threshold voltage should
also decrease.
MOS transistors are
treated as switches and
many times they are bad
switches because of
various leakage current.
• Subthreshold leakage
• gate leakage
Variation of different leakage
• Source-Substrate and
components with technology
Drain-Substrate band to generation and oxide thickness
band tunneling (b) doping profile. [1]
leakage(BTBT)

Vt scaling increases subthreshold leakage exponentially, tox is

reduced so gate current increases, increasing doping increases
BTBT.
Sub threshold leakage power
will be on the order of several
hundreds of watts beyond
90nm.

Subthreshold leakage power

is approaching practical limit
of 50% of supply voltage

Pentium 4 at 3.2Ghz 75 watts

at 1.4v. Itanium 2 is about
100 watt
So although transistor performance continues to increase albeit at
a slower rate than in the past, energy consumed per logic function
will not go down at the rate as it used to be.

Gate tunneling is due to the tunneling of electrons from conduction

band of bulk silicon and source, drain to the gate electrode.
Subthreshold voltage is due to the diffusion of carriers from source
to drain.
BTBT is basically reversed biased junction current.

In the present day technology

gate leakage and BTBT have
become dominant leakage
current. They also vary with
temp.
So although transistor performance will continue to increase albeit
at a slower rate than in the past energy consumed per logic
function will not go down at the rate as it used to be.

Earlier interconnection were considered as the limiter of

performance but now for giga-scale chip power and energy
is the limiter.

Innovations have to be made at device, technology, material

and design level to achieve TIPS performance.
Application and system software should be able to exploit it.
Combinational circuit are non-regenerative—not dependent
upon previously applied inputs. No feed back.
Regenerative circuit: Feed back between output and input.

Bistable : two stable states or operating mode. Each of one is attained under
certain input/output conditions

Monostable: Has only one operating point, On externally disturbed,

produces an output and after certain duration returns to the stable point
Astable: No stable level of operation—ring oscillator.
Happy Deepawali

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