Name – Shaurya Lalwalia

Roll N0. – 04020902718

Semester – 3rd Sem

Branch - CSE
 Sequential Circuits
Digital Logic | Introduction of Sequential Circuits
A Sequential circuit combinational logic circuit that consists of inputs
variable (X), logic gates (Computational circuit), and output variable (Z).

Combinational circuit produces an output based on input variable only, but

Sequential circuit produces an output based on current input and previous input
variables. That means sequential circuits include memory elements which are
capable of storing binary information. That binary information defines the state of
the sequential circuit at that time. A latch capable of storing one bit of information.
 Types of Sequential Circuits
1) Asynchronous sequential circuit – These circuit do not use a clock
signal but uses the pulses of the inputs. These circuits
are faster than synchronous sequential circuits because there is
clock pulse and change their state immediately when there is a
change in the input signal. We use asynchronous sequential circuits
when speed of operation is important and independent of internal
clock pulse. But these circuits are more difficult to design and their
output is uncertain.
2) Synchronous sequential circuit – These circuit uses clock signal and level
inputs (or pulsed) (with restrictions on pulse width and circuit
propagation). The output pulse is the same duration as the clock pulse for
the clocked sequential circuits. Since they wait for the next clock pulse to
arrive to perform the next operation, so these circuits are
bit slower compared to asynchronous. Level output changes state at the
start of an input pulse and remains in that until the next input or clock
pulse. We use synchronous sequential circuit in synchronous counters, flip
flops, and in the design of MOORE-MEALY state management machines.
Differences between Synchronous and
Asynchronous Counter
S No. SYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER

In synchronous counter, all flip flops are In asynchronous counter,

1) triggered with same clock different flip flops are triggered
simultaneously. with different clock, not
simultaneously.

Synchronous Counter is faster than Asynchronous Counter is slower

2) asynchronous counter in operation. than synchronous counter in
operation.
3) Synchronous Counter does not Asynchronous Counter produces
produce any decoding errors. decoding error.

4) Synchronous Counter is also called Asynchronous Counter is also called

Serial Counter. Parallel Counter.

5) Synchronous Counter designing as Asynchronous Counter designing as

well implementation are complex well as implementation is very easy.
due to increasing the number of
states.

6) Synchronous Counter will operate in Asynchronous Counter will operate

any desired count sequence. only in fixed count sequence
(UP/DOWN).

7) Synchronous Counter examples Asynchronous Counter examples

are: Ring counter, Johnson counter. are: Ripple UP counter, Ripple DOWN
counter.
Synchronous Counter Design
Asynchronous Counter Design
 Types of Synchronous Counters

 Binary
BCD
Decade
Up/Down
Synchronous Decade Counters
Synchronous counter counts from 0-9 similar to asynchronous counter and
then again recycles zero. This process is done by driving the 1010 states
back to the 0000 state. This is termed as truncated sequence, that can be
designed by the below circuit.
• From the series on the left table, we can observe that
• Q0 ties on each and every CLK pulse
• Q1 alters on the next clock pulse every time when Q0=1 &
Q3=0.
• Q2 alters on the next clock pulse every time when Q0=Q1=1.
• Q3 alters on the next CLK pulse each and every time when
Q0=1, Q1=1 & Q2=1 (count 7), or when Q0=1 & Q3=1 (count
9).
 Synchronous Up-Down Counters
A three bit synchronous Up-Down counter, tabular form and series are
given below. This type of counter has an up-down control i/p similar to
asynchronous up-down counter, that is used to control the counter’s
direction through a certain series.
 The series of the table shows
• Q0 ties on each CLK pulse for both up & down series
• When Q0=1 for the up series, then the state of the Q1 changes on
the next CLK pulse.
• When Q0=0 for the down series, then the state of the Q1 changes
on the next CLK pulse.
• When Q0=Q1=1 for the up series, then the state of the Q2 changes
on the next CLK pulse.
• When Q0=Q1=0 for the down series, then the state of the Q2
changes on the next CLK pulse.
 Types of Asynchronous Counters

 Binary
BCD
Decade
Up/Down
 Asynchronous Decade Counters
In the previous counter have 2n states. But, counters with states less than 2n is
also possible. These are designed to have the no. of states in their series.
These are called shortened sequences which are accomplished by driving the
counter to recycle before going through all of its states. A common modulus
for counters with shortened sequence is 10. A counter with 10-states in its
series is called a decade counter . The implemented decade counter circuit is
given below.
When the counter counts to ten, then all the FFs will be cleared. Notice
that only Q1&Q3 both are used to decode the count of 10, that is called
partial decoding. At the same time one of the other states from 0-9 have
both Q1&Q3 will be high. The series of the decade counter table is given
below.
 Asynchronous Up-Down Counters

In particular applications, a counter must be capable to count both up

& down. The below circuit is a three bit up & down counter, that
counts UP or DOWN based on the control signal status. When the UP
i/p is at 1 & the DOWN i/p is at 0, the NAND gate between FF0 & FF1
will gate the non-inverted o/p (Q) of flip flop (FF0) into the clock i/p of
flip flop (FF1). Likewise, the non-inverted o/p of Flip Flop1 will be gated
through the other NAND gate into the clock i/p of flip-flop2. Therefore
the counter will count up.
Once the control i/p (UP) is at 0 & DOWN is at 1, the inverted o/ps
of flip-flop0 (FF0) and flip-flop1 (FF) are gated into the clock i/ps of
FF1 & FF2 separately. If the FFs are initially changed to 0’s, then the
counter will go through the below series as i/p pulses are applied.
Notice that an asynchronous up-down counter is slower than an UP
counter/down counter because of an extra propagation delay
introduced by the NAND gates.