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Abstract
Introduction
Block Diagram
Operation
Advantages
Applications
ABSTRACT
Multilevel inverter has a capability of handling high voltage high power with
less harmonic distortion.
The main object of this is to increase number of voltage levels with a low
number of switches and source output without adding any complexity to
the power circuit.
The main merit of the new topology is to reduce the lower total harmonic
distortion, lower electromagnetic interference and high output voltage.
A multilevel inverter not only achieves high power ratings but also
improves the performance of the whole system in terms of harmonics,
DV/DT stresses and stress in bearing of motors.
INTRODUCTION:
The concept of multilevel inverter has been introduced since 1975.
In recent years multilevel inverter has drawn a great attention in industry, due
to use in high power and high voltage applications.
Multilevel inverter basically starts with three-voltage levels. That can be used in
high power medium voltage application.
The two levels inverter such as low switching frequency hence reduction in
switching losses, lower harmonics, low common mode voltage.
Multilevel inverter has some drawback that , by increasing the number of
voltage levels, higher number of semiconductor switches are required with
separate gate driver circuit.
Different pulse width modulation techniques are used to control the output
voltage with multilevel inverter.
The conventional multilevel inverter topology can be classified into 3 types.
They are
1. Diode clamped multilevel inverter
2. Flying capacitor multilevel inverter
3. Cascade H-Bridge multilevel inverter
BLOCK DIAGRAM:
Figure: single phase7-Level Multilevel Inverter with Converting Its Optimal Structure
OPREATION:
The block diagram of multilevel inverter using optimization
topology is shown in figure.
In this figure the right side h-bridge is connected which is used to
generate the required positive level is called positive level generator
and also generate negative level is called negative level generator.
The main purpose of this is to minimize the total harmonic
distortion with different PWM technique using optimization topology
and is to minimize power semiconductor switches then conventional
multilevel inverter.
Switches T7,T8,T9 and T10 are used for complementary pair.
When T7,T10 are turned ON together, positive half cycle (level
+1,+2,+3) can be generated.
When T8,T9 are turned ON together, negative half cycle (level -1,-
2,-3) are generated.
The multilevel inverter can operates in different modes are given
below
MODES OF OPERATION FOR POSITIVE
LEVEL GENERATORS:
MODE-0:
When switches T6,T7 and T10 are turned ON.
Then the output voltage is 0.
MODE-1:
When switches T1,T2,T4,T7 and T10 are turned ON
Then the output voltage is “Vdc”.
MODE-3:
When switches T3,T5,T7 and T10 are turned ON.
Then the output voltage is “3Vdc”.
MODE-5:
When switches T3,T4,T8,T9 are turned ON.
Then the output voltage is “-2Vdc”.