22.power MOSFET

Lecture Notes
Power MOSFETs
Outline
• Construction of power MOSFETs
• Physical operations of MOSFETs
• Power MOSFET switching Characteristics
• Factors limiting operating specfications of MOSFETs
• COOLMOS
• PSPICE and other simulation models for MOSFETs
Copyright © by John Wiley & Sons 2003

MOSFETs - 1
Multi-cell Vertical Diffused Power MOSFET (VDMOS)

MOSFETs - 2
Important Structural Features of VDMOS
source gate conductor

body-source
field oxide
short
gate oxide
N+ N+ N+ N+
P (body) P (body)
N- parasitic i
D
channel
(drift region) BJT length
integral
N+ diode
drain
1. Parasitic BJT. Held in cutoff by body-source short

2. Integral anti-parallel diode. Formed from parasitic BJT.
3. Extension of gate metallization over drain drift region. Field plate and accumulation
layer functions.
4. Division of source into many small areas connected electrically in parallel.
Maximizes gate width-to-channel length ratio in order to increase gain.
5. Lightly doped drain drift region. Determines blocking voltage rating.

MOSFETs - 3
Alternative Power MOSFET Geometries
Source
boddy-source short
Oxide
N+ N+
Gate
Channel
conductor P
P
length • Trench-gate MOSFET
Parasitic BJT N- Integral
ID ID
diode • Newest geometry. Lowest
N+ on-state resistance.
Drain
• V-groove MOSFET.
• First practical power
MOSFET.
• Higher on-state
resistance.

MOSFETs - 4
MOSFET I-V Characteristics and Circuit Symbols
i
D [v - V = v ]
GS GS(th) DS
ohmic
V
GS5
active
V GS4
V
GS3
V
GS2
V
GS1
v
V < V DS
GS GS(th) BV
DSS

MOSFETs - 5
The Field Effect - Basis of MOSFET Operation
V
GG3
V
GG1 +
+ SiO
SiO 2
2 + + + + + + + + + + +
+ + + + + + + + + + +
+ +
N N
ionized P
depletion layer
acceptors
P boundary inversion layer
ionized with free electrons
N acceptors
V N depletion layer boundary

GG2
+
SiO
2
+ + + + + + + + + + + • V al ue d e t e r m i ne d b y se v e r al f act o r s
1 . Ty p e o f m at e r i al use d f o r g at e co nd uct o r
+ 2 . Do p i ng d e nsi t y o f b o d y r e g i o n d i r e ct l y
N
b e ne at h g at e
ionized depletion layer 3 . Im p ur i t i e s/ b o und char g e s i n o x i d e
P acceptors boundary o x
free electrons
4 . Ox i d e cap aci t ance p e r uni t ar e a Co x =
N t ox
t o x = o x i d e t hi ck ne ss
Thr e sho l d V o l t ag e V GS( t h)

• A d j ust t hr e sho l d v o l t ag e d ur i ng d e v i ce
• V GS whe r e st r o ng i nv e r si o n l ay e r has f o r m e d . f ab r i cat i o n v i a an i o n i m p l ant at i o n o f
i m p ur i t i e s i nt o b o d y r e g i o n j ust b e ne at h
Ty p i cal v al ue s 2 - 5 v o l t s i n p o we r MOSFETs
g at e o x i d e .

MOSFETs - 6
Drift Velocity Saturation
electron
drift velocity
• Mobilit y also decreases because large
8x10 6
v alues of V GS increase free elect ron
cm/s ec densit y .
• At larger carrier densit ies, free carriers

collide wit h each ot her ( carrier-carrier
4 electric
1.5x10 V/cm field scat t ering) more oft en t han wit h lat t ice and
mobilit y decreases as a result .
• In MOSFET channel, J = q µn n E
• Mobilt y decreases, especially v ia carrier-
= q n v n ; v elocit y v n = µn E
carrier scat t ering leead t o linear t ransfer
curv e in power dev ices inst ead of square
• Velocit y sat urat ion means t hat t he law t ransfer curv e of logic lev el MOSFETs.
mobilit y µn inv ersely proport ional t o
elect ric field E.
MOSFETs - 7
Channel-to-Source Voltage Drop
• V GS = V GG = V ox + V CS( x) ;
V + V CS( x) = ID1 RCS( x)
GG V
+ DD1 I
D1
V ox(x) • Larger x v alue corresponds be being

closer t o t he drain and t o a smaller
V (x) inversion
N
+
CS V ox .
x depletion
P
• Smaller V ox corresponds t o a smaller
N channel t hickness. Hence reduct ion in
N + channel t hickness as drain is
approached from t he source.

MOSFETs - 8
Channel Pinch-off at Large Drain Current
• A ppar ent di l emma of
channel di sappear i ng at
+
V DD2 + I
D2 dr ai n end f or l ar ge I D
av oi ded.
V V ox(x)
GG
1. Lar ge el ect r i c f i el d at dr ai n
V (x) inversion
+ end or i ent ed par al l el t o
N CS
depletion dr ai n cur r ent f l ow. A r i ses
x
velocity f r om l ar ge cur r ent f l ow i n
saturation channel const r i ct i on at
P region dr ai n.
N
+ 2. Thi s el ect r i c f i el d t ak es
N
ov er mai nt enance of
mi ni mum i nv er si on l ay er
t hi ck ness at dr ai n end.
• I D2 > I D1 so V CS2 (x ) > V CS1 (x ) and t hus channel
nar r ower at an gi v en poi nt . • Lar ger gat e- sour ce bi as
V GG post pones f l at t eni ng
• Tot al channel r esi st ance f r om dr ai n t o sour ce of I D v s V DS unt i l l ar ger
i ncr easi ng and cur v e of I D v s V DS f or a f i x ed V GS
v al ues of dr ai n cur r ent ar e
f l at t ens out . r eached.
MOSFETs - 9
MOSFET Switching Models for Buck Converter
Vd
D
Io
r
D DS(on)
F
RG
C
gd
+ G
V
GG
C
gs
S
• Buck converter using power MOSFET.
D
• MOSFET equivalent circuit valid for
on-state (triode) region operation.
C
gd
G I = f(V )
D GS
C
gs
• MOSFET equivalent circuit valid for off-
S state (cutoff) and active region operation.
MOSFETs - 10
MOSFET Capacitances Determining Switching Speed
C
gd
C
gd2 idealization
actual
C gd1
v
v = v 200 V DS
GS DS
• Gate-source capacitance Cgs approximately

constant and independent of applied voltages.
• Gate-drain capacitance C gd varies with applied

voltage. Variation due to growth of depletion layer
thickness until inversion layer is formed.
MOSFETs - 11
Internal Capacitances Vs Spec Sheet Capacitances
MOSFET internal capacitances Reverse transfer or feedback capacitance
C gd C
bridge
G D
+V -
C gs Cds b
S C gd
Bridge balanced (Vb=0) Cbridge = Cgd = C rss

Input capacitance
G D Output capacitance
G D
Ciss
S
C oss
S
Ciss = C gs + C gd
C oss = C gd + Cds
MOSFETs - 12
Turn-on Equivalent Circuits for MOSFET Buck Converter
V in V in
• Equi val ent ci r cui t • Equi val ent ci r cui t
dur i ng t d(on) . dur i ng t r i .
D I o
F D I o
F
C
DC C
R C gd1 DC
G R C gd1
G
+
V i
G +
GG C V
gs i
GG G C
gs
V
• Equi val ent ci r cui t • Equi val ent ci r cui t in
V in
dur i ng t f v1 . dur i ng t f v2 .
I o I o r
DS(on)
R
G
R C gd1
G +
V i C
G gs
+ GG C gd2
V i
GG G

MOSFETs - 13
MOSFET-based Buck Converter Turn-on Waveforms
• Free-wheeling diode
assumed to be ideal.
(no reverse recovery
current).

MOSFETs - 14
Turn-on Gate Charge Characteristic
V
V V d
gs d1 Vd2
Vgs,on
I
I V D1
d3 C
V + D1 gd
t g
mo + +
Specified I Vgs C C V
D1 gs ds ds
- -
Qgate g (V gs- V )
Q Q m t
on p
Vgs V + I /g m
Q t D1
(Vt+ID1/gm) T1
V
Qon =  t
 [Cgs(Vgs) + Cgd(Vgs)] Vgs dVgs t
Vgs,off Vgs,off V
gs,on
Vds,on I
d
 I
Qp =  Cgd(Vds) Vds dVds D1
t
Vd
V
Vgs,on ds
QT = Qon + Qp + 
 [Cgs(Vgs) + Cgd(Vgs)] Vgs dVgs V
V ds,on
(Vt+ID1/gm) d
t
MOSFETs - 15
Turn-on Waveforms with Non-ideal Free-wheeling Diode
V in
Io i D(t)
F
I o+ I rr
I rr t
C gd1
I rr R
G
i (t)
D +
t rr Io V i
GG G C gs
t t
ri
V
GS,I • Equivalent circuit for
V
GS(th)
o
estimating effect of free-
t wheeling diode reverse
recovery.
V in v (t)
DS
t
MOSFETs - 16
MOSFET-based Buck Converter Turn-off Waveforms
 2 = R G(C +C )
gd2 gs
v (t)
GS 1 = R G(C +C )
gd1 gs • A ssume i deal f r ee-
V
GG V V
GS(th)
w heel i ng di ode.
GS,I
o
• Essent i al l y t he
t i nver se of t he t ur n- on
i (t)
G
pr ocess.
t
d(off)
v (t)
DS • Model quani t at i vel y
i (t)
D usi ng t he same
Io
V
in equi val ent ci r cui t s as
f or t ur n- on. Si mpl y
use cor r ect dr i vi ng
t vol t ages and i ni t i al
t
rv2
t
rv1 t condi t i ons
fi

MOSFETs - 17
dV/dt Limits to Prevent Parasitic BJT Turn-on
gate D
source
C
G gd
N
+ N + paras itic
BJT
P P
C gd
N
+
N S
dV DS
drain
• Large posit iv e Cgd
dt
could t urn on parasit ic BJT.
D
L+
• Turn-on of T+ and rev erse recov ery of Df - will
D
F+ dv DS
T+ produce large posit iv e Cgd in bridge circuit .
I
o dt
D
L- • Parasit ic BJT in T- likely t o hav e been in rev erse
act iv e mode when Df - was carry ing current . Thus
T-
D F- st ored charge already in base which will increase
dv DS
likey hood of BJT t urn-on when posit iv e Cgd is
dt
generat ed.
MOSFETs - 18
Maximum Gate-Source Voltage
• V GS(max) = maxi mum per mi ssi bl e gat e-
sour ce vol t age.
• If V GS >V GS(max) r upt ur e of gat e oxi de by

l ar ge el ect r i c f i el ds possi bl e.
• EBD(oxi de) - 5 - 1 0 mi l l i on V / cm
• Gat e oxi de t y pi cal l y 1 0 0 0 anst r oms t hi ck
• V GS(max) < [ 5 x1 0 6 ] [ 1 0 - 5 ] = 5 0 V
• Ty pi cal V GS(max) 2 0 - 3 0 V
• St at i c char ge on gat e conduct or can r upt ur e

gat e oxi de
• Handl e MOSFETs w i t h car e (gr ound
y our sel f bef or e handl i ng devi ce)
• Pl ace ant i - par al l el connect ed Zener di odes
bet w een gat e and sour ce as a pr ot ect i ve
measur e

MOSFETs - 19
MOSFET Breakdown Voltage
depletion layer boundary depletion layer boundary
without field plate with field plate action
action of gate electrode of gate electrode
+ +
N N N
P P
+
N
• BV DSS = drain-source breakdown

2 . Appropriat e lengt h of drain drift region
v olt age wit h V GS = 0
• Caused by av alanche breakdown of

3 . Field plat e act ion of gat e conduct or
drain-body junct ion ov erlap of drain region
• Achiev e large v alues by 4 . Prev ent t urn-on of parasit ic BJT wit h

body -source short ( ot herwise BV DSS
1 . A v oidance of drain-source reach-
t hrough by heav y doping of body = BV CEO inst ead of BV CBO)
and light doping of drain drif t region

MOSFETs - 20
MOSFET On-state Losses
source gate
accumulation
channel layer
resistance resistance
+
N N+
P
P
I drift region
source region D resistance
N
resistance
drain region
+ resistance
N
drain
• On-st at e power dissipat ion Pon = • r DS( on) dominat ed by drain drif t resist ance
f or BV DSS > f ew 1 0 0 V
Io 2 r DS( on)
Vd BV DSS2
• r DS( on) = - 3 x1 0 -7
ID A
• Large V GS minimizes accumulat ion
• r DS( on) increases as t emperat ure increases.
lay er resist ance and channel
Due t o decrease in carrier mobilit y wit h
resist ance increasing t emperat ure.

MOSFETs - 21
Paralleling of MOSFETs
• MOSFETs can be easily Rd
paralleled because of Q
1
posit iv e t emperat ure G
coefficient of r DS( on) .
• Posit iv e t emperat ure coefficient leads t o t hermal

st abilizat ion effect .
• If r DS( on) 1 > r DS( on) 2 t hen more current and t hus
higher power dissipat ion in Q2 .
• Temperat ure of Q2 t hus increases more t han

t emperat ure of Q1 and r DS( on) v alues become
equalized.
MOSFETs - 22
MOSFET Safe Operating Area (SOA)
• No di st i nct i on bet w een

FBSOA and RBSOA . SOA
i s squar e.
• FB = f or w ar d bi as.
V GS • 0 .
• RB = r ever se bi as.
V GS Š 0 .
• No second br eakdow n.

MOSFETs - 23
Structural Comparison: VDMOS Versus COOLMOS™
• Conventional
vertically oriented
power MOSFET
source gate
cond
uctor
• COOLMOS™ structure
N+ N+ N+ N+
P P (composite buffer structure,
b b
W super-junction MOSFET,
P N P super multi-resurf
MOSFET)
b b b
• Vertical P and N regions of
width b doped at same
N+ density (Na = Nd)
drain
MOSFETs - 24
COOLMOS™ Operation in Blocking State
source
gate
cond • COOLMOS™ structure partially
depleted.
uctor
N+ N+ N+ P N+
P
b b
• Arrows indicate direction of
depletion layer growth as device
N
P V
-
turns off.
P 1
+
• Note n-type drift region and
N+ adjacent p-type stripes deplete
drain uniformly along entire vertical
length.
source
gate
cond • COOLMOS™ structure at edge
uctor
of full depletion with applied
N+
P
N+ N+
P
N+ voltage Vc. Depletion layer
b N b
reaches to middle of vertical P
and N regions at b/2.
Ec Ec -
P P
Vc • Using step junction formalism,
+ Vc = (q b2 Nd)/(4 ) = b Ec,max/2
N+
• Keep Ec,max ≤ EBD/2. Thus
drain
Nd ≤ (  EBD)/(q b)

MOSFETs - 25
COOLMOS™ Operation in Blocking State (cont.)
• For applied voltages V > Vc, vertically oriented electric field Ev begins to grow in depletion region.
• Ev spatially uniform since space charge compensated for by Ec. Ev ≈ V/W for V >> Vc.
• Doping level Nd in n-type drift region can be much greater than in drift region of conventional
VDMOS drift region of similar BVBD capability.
• At breakdown Ev = EBD ≈ 300 kV/cm ; V = BVBD = EBDW

MOSFETs - 26
COOLMOS™ Operation in ON-State
source
gate
cond
uctor
• On-state specific resistance ARon [Ω-cm2]
N+ N+ R N+ N+
P on P much less than comparable VDMOS
b b because of higher drift region doping.
P P -
V • COOLMOS™ conduction losses much
N 1
+
less than comparable VDMOS.
N+
drain
I R
D L
• Ron A = W/(q µnNd) ; Recall that Nd = ( EBD)/(q b)
• Breakdown voltage requirements set W = BVBD/ EBD.
• Substituting for W and Nd yields Ron A = (b BVBD)/( µn EBD2)

MOSFETs - 27
Ron A Comparison: VDMOS versus COOLMOS™
• COOLMOS at BVBD = 1000 V. Assume b ≈ 10 µm. Use EBD = 300 kV/cm.

• Ron A = (10-3 cm) (1000 V)/[ (9x10-14 F/cm)(12)(1500 cm2 -V-sec)(300 kV/cm)2]
Ron A = 0.014 Ω-cm . Corresponds to Nd = 4x1015 cm-3
• Typical VDMOS, Ron A = 3x10-7 (BVBD)2

• Ron A = 3x10-7 (1000)2 = 0.3 Ω-cm ; Corresponding Nd= 1014 cm3
• Ratio COOLMOS to VDMOS specific resistance = 0.007/0.3 = 0.023 or approximately 1/40

• At BVBD = 600 V, ratio = 1/26.
• Experimentally at BVBD = 600 V, ratio is 1/5.
• For more complete analysis see: Antonio G.M. Strollo and Ettore Napoli, “Optimal ON-Resistance
Versus Breakdown Voltage Tradeoff in Superjunction Power Device: A Novel Analytical Model”, IEEE
Trans. On Electron Devices,Vol. 48, No. 9, pp 2161-2167, (Sept., 2001)

MOSFETs - 28
COOLMOS™ Switching Behavior
• Larger blocking voltages Vds > depletion
• MOSFET witching waveforms for clamped inductive load. voltage Vc, COOLMOS has smaller Cgs, Cgd,
and Cds than comparable (same Ron and
BVDSS) VDMOS.
• Small blocking voltages Vds < depletion

v (t)
voltage Vc, COOLMOS has larger Cgs, Cgd,
GS V GS,Io
and Cds than comparable (same Ron and
V BVDSS) VDMOS.
GS(th)
t
• Effect on COOLMOS switching times
relative to VDMOS switching times.
v (t) V
DS V DS(on) • Turn-on delay time - shorter
d
• Current rise time - shorter
t
• Voltage fall time1 - shorter
t d(on) t
ri
t
fv1
t
fv2 t d(off)
t rv1 t fi • Voltage fall time2 - longer
• Turn-off delay time - longer
i (t)
D Io t • Voltage rise time1 - longer
rv2
• Voltage rise time2 - shorter
t • Current fall time - shorter
MOSFETs - 29
PSPICE Built-in MOSFET Model
Circuit compon ents
• RG, RDS, RS, RB, and RD = parasitic

ohmic resistances
• Cgs Cgd, and Cgb = constant volt age-

independen t capacitors
• Cbs and Cbd = nonlinear voltage-

dependent cap acitors (depl etion layer
capacitances)
• Idrain = f(Vgs, Vds) accounts for dc

characteristics of MOSFET
• Model deve loped for lateral (signal level)

MOSFETs
MOSFETs - 30
Lateral (Signal level) MOSFET
• Body-source short keeps Cbs constant.
• Body-source short puts C bd between drain and

source.
• Variations in drain-source voltage relatively

small, so change s in Cbd also relatively small.
• Capacitances relatively independ ent of terminal

• Cgs, Cbg , Cgd due to electrostatic
voltages
capacitance of gate oxide. Independ ent
of applied voltage
• Consequently PSPICE MOSFET model ha s
voltage-independen t capacitances.
• Cbs and Cbd due to depletion laye rs.
Capacitance va ries with junction voltage.
MOSFETs - 31
Vertical Power MOSFET
• Drain-drift region and large drain-source

voltage va riations cause large variations in • MOSFET circuit simulation
drain-body dep letion laye r thickne ss
models must take this variation
into account.
• Large change s in Cgd with change s in drain-source
voltage. 10 to 100:1 change s in C gd measured in high
voltage MOSFETs.
• Moderate change s in Cgb and Cbs.

MOSFETs - 32
Inadequacies of PSPICE MOSFET Model
4
MTP3055E
V = 0
C gd GS • Cgs and Cgd in PSPICE model a re
[nF] constant independ ent of t erminal voltages
2 SPICE model
• In vertical power MOSFETs, Cgd varies

Motorola subcircuit model substantially with terminal voltages.
0
0V 10V 20V 30V
V
DS
60V
MTP3055E V
DS
• Comparison of transient response of drain-
40V
source voltage using PSPICE model and
Motorola SPICE an improved subcircuit model. Both
20V subcircuit model models used in same step-down conv erter
model circuit.
0V
0s 100ns 200ns 300ns
Time

MOSFETs - 33
Example of an Improved MOSFET Model
• Developed by Motorola for their TMOS line of
power MOSFETs
Drain • M1 uses built-in PSPICE models to describe

dc MOSFET characteristics. Space charge
LDRAIN capacitances of intrinsic model set to zero.
DGD
CGDMAX • Space charge capacitance of DGD models
RDRAIN1 voltage-dependent gate-drain capacitance.
RGDMAX RDRAIN2
• CGDMAX insures that gate-drain capacitance
does not get unrealistically large at very low
LGATE RGATE DBODY
drain voltages.
M1 • DBODY models built-in anti-parallel diode
Gate CGS inherent in the MOSFET structure.
RDBODY
RSOURCE • CGS models gate-source capacitance of
MOSFET. Voltage dependence of this
LSOURCE capacitance ignored in this model.
• Resistances and inductances model parasitic
Source components due to packaging.
• Many other models described in literature. Too
numerous to list here.
MOSFETs - 34
Another Improved MOSFET Simulation Model
• M2 and M3 are SPICE level 2
MOSFETs used along with Voffset to
model voltage dependent beh avior of
Cgd.
• JFET Q 1 and Rd account for voltage d rop

in N- drain drift region
• Dsub is built-in SPICE diode model used

to account for parasitic anti-parallel diode
in MOSFET structure.
• Reference - "An Accurate Model for

Power DMOSFETs Including Inter-
electrode Capacitances", Robert Scott,
Gerhard A. Frantz, and Jennifer L.
• LG, RG, LS RS, LD, RD - parasitic Johnson , IEEE Trans. on Power
inductances and resistances Electronics, Vol. 6, No. 2, pp. 192-198,
(April, 1991)
• M1= intrinsic SPICE level 2 MOSFET with no
parasitic resistances or capacitances.
MOSFETs - 35

22.power MOSFET

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Lecture Notes

Copyright © by John Wiley & Sons 2003

Copyright © by John Wiley & Sons 2003

source gate conductor

1. Parasitic BJT. Held in cutoff by body-source short

Copyright © by John Wiley & Sons 2003

Copyright © by John Wiley & Sons 2003

Copyright © by John Wiley & Sons 2003

V N depletion layer boundary

Thr e sho l d V o l t ag e V GS( t h)

Copyright © by John Wiley & Sons 2003

• At larger carrier densit ies, free carriers

V ox(x) • Larger x v alue corresponds be being

Copyright © by John Wiley & Sons 2003

• Gate-source capacitance Cgs approximately

• Gate-drain capacitance C gd varies with applied

MOSFET internal capacitances Reverse transfer or feedback capacitance

Bridge balanced (Vb=0) Cbridge = Cgd = C rss

Copyright © by John Wiley & Sons 2003

Copyright © by John Wiley & Sons 2003

Copyright © by John Wiley & Sons 2003

• If V GS >V GS(max) r upt ur e of gat e oxi de by

• St at i c char ge on gat e conduct or can r upt ur e

Copyright © by John Wiley & Sons 2003

• BV DSS = drain-source breakdown

• Caused by av alanche breakdown of

• Achiev e large v alues by 4 . Prev ent t urn-on of parasit ic BJT wit h

Copyright © by John Wiley & Sons 2003

Copyright © by John Wiley & Sons 2003

• MOSFETs can be easily Rd

• Posit iv e t emperat ure coefficient leads t o t hermal

• Temperat ure of Q2 t hus increases more t han

• No di st i nct i on bet w een

Copyright © by John Wiley & Sons 2003

Copyright © by John Wiley & Sons 2003

• At breakdown Ev = EBD ≈ 300 kV/cm ; V = BVBD = EBDW

• Ron A = W/(q µnNd) ; Recall that Nd = ( EBD)/(q b)

• Breakdown voltage requirements set W = BVBD/ EBD.

• Substituting for W and Nd yields Ron A = (b BVBD)/( µn EBD2)

Copyright © by John Wiley & Sons 2003

• COOLMOS at BVBD = 1000 V. Assume b ≈ 10 µm. Use EBD = 300 kV/cm.

• Typical VDMOS, Ron A = 3x10-7 (BVBD)2

• Ratio COOLMOS to VDMOS specific resistance = 0.007/0.3 = 0.023 or approximately 1/40

Copyright © by John Wiley & Sons 2003

• Small blocking voltages Vds < depletion

Circuit compon ents

• RG, RDS, RS, RB, and RD = parasitic

• Cgs Cgd, and Cgb = constant volt age-

• Cbs and Cbd = nonlinear voltage-

• Idrain = f(Vgs, Vds) accounts for dc

• Model deve loped for lateral (signal level)

• Body-source short keeps Cbs constant.

• Body-source short puts C bd between drain and

• Variations in drain-source voltage relatively

• Capacitances relatively independ ent of terminal

• Drain-drift region and large drain-source

• Moderate change s in Cgb and Cbs.

• In vertical power MOSFETs, Cgd varies

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Drain • M1 uses built-in PSPICE models to describe

• JFET Q 1 and Rd account for voltage d rop

• Dsub is built-in SPICE diode model used

• Reference - "An Accurate Model for

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