A Column-Oriented Memory Controller (CONCEPT)

for Efficient Memory and PIM Operations in RRAM

Presented By
G .Indira,
18331D5707
Under the guidance of
B. Srinivas M.Tech., (Ph.D),
Assistant Professor, dept of ECE

Maharaja Vijayaram Gajapathi Raj College of Engineering(A)

APPROVED by AICTE,NEW DELHI &Affiliated to JNTU,KAKINADA
Reaccredited by NBA,NAAC with ‘A’ grade

1
 Table of contents
 Abstract
 Introduction
 Classification of memory
 DRAM
 Von Neumann Bottleneck
 RRAM
 Why a New Memory Controller for RRAM?
 Concept Design
 Topics to be discussed in next presentation:
 References
 Abstract
• DRAM cannot easily scale below a 20-nm technology node.

• While RRAM having less scalability issues below 20-nm technology.

• Moreover, RRAM’s resistivity enables its use for processing-in-memory

(PIM), potentially alleviating the von Neumann bottleneck.

• Because of technological issues, existing DRAM-centric memory

controllers cannot exploit the full potential of resistive RAM (RRAM).

• The design of a memory controller called CONCEPT.

• The controller is optimized to exploit unique properties of RRAM to

enhance its performance and energy efficiency as well as exploiting
RRAM’s PIM capability.
 Introduction
Memory:

 Memory is internal storage areas in the computer system.

 The term memory identifies data storage that comes in the form of chips,
and the word storage is used for memory that exists on tapes or disks.
 Classification of memory
PRIMARY MEMORY

RAM ROM

SRAM DRAM ROM EPROM

Fig1: classification of memory

 DRAM
 DRAM is a type of RAM that stores each bit of data on a separate
capacitor.

 This is an efficient way to store data in memory, because it requires less

physical space to store the same amount of data .

 DRAM is used for main memory.

Fig2: structure od DRAM cell

 Operation of DRAM
 DRAM cell is one transistor, one capacitor cell structure . The cell are
arrange in a rectangular grid like array.

 Transistor acting like a switch. If the transistor is closed the current is flow
in the circuit.

 If the transistor is open the not current will flow the circuit . stores data as
charge on capacitors.

 If capacitor is charged the is 1, else the is 0

.
 Needs refreshing cycle as capacitors have a tendency of discharging.

 The term dynamic refers to this tendency of the stored charge to leak away,
even with power continuously applied.
 DRAM is Volatile memory
 Von Neumann Bottleneck

CPU

CONTROL
UNIT

ALU OUTPUT
INPUT DEVICE
DEVICE

REGISTER

MEMORY UNIT

Fig:2 Architecture of Von Neumann

Bottleneck
 memory of von neumann architecture

 It was the machine developed by john neumann in 1940at Princeton

university.

 Hence it is also known as von neumann machine. It is based on stored

program concept.

 A stored program computer consists of a processing unit ad attached

memory system.

 CPU
The CPU is the electronic circuit responsible for executing the
instructions of a computer program.
 Contd.,

 Control unit : The control unit controls the operation of the ALU.

 ALU:
 The ALU allows arithmetic operations to be performed.

 BUSES:
 Buses means the data is to be transmitted from one part of a
computer to another, connecting all major internal components to the cpu
and memory.

 Memory unit:
 The memory unit consist of RAM. This memory is fast and
also directly accessible by the CPU
 What is RRAM

 RRAM, also known as RRAM (resistive random access memory), is

a form of nonvolatile storage.

 That operates by changing the resistance of a specially formulated

solid dielectric material.

 It is also called as ReRAM. Resistive Random Access Memory is a

promising technology designed with high density in memory
computations.

 RRAM is a type of memistor technology.

 Memistor regulates the flow of electrical current that works by

changing the resistance across a die electric solid state material.
 Structure of RRAM

• It is a two terminal passive device in which an insulating switching layer is

sandwiched conducting electrodes.
• RRAM device is fabricated using a metal-insulator-metal(MIM)structure.
where the insulator is rich in oxygen ions.

Fig:3 Structure of RRAM Cell

Operation of RRAM

Fig:4 Operation of RRAM

 It is MIM structure where metal oxide material is sandwiched between two

electrodes.

 When positive voltage is applied to the top electrode it forms conductive filament
between two electrodes. Where the filament contains oxygen ions .This is in ON
STATE.

 When negative voltage is applied on the bottom electrode the conductive filament
will break then there is no connection between two electrodes. This is in OFF
STATE.

 In RRAM voltage is applied to metal stack creating a change in the resistance that
records the data(0&1) in the memory.
SWITCHING MECHANISM OF RRAM

Fig:5 Unipolar and Bipolar switching mechanism

 RRAM have two switching mechanisms. There are unipolar and
bipolar switching mechanism.

 RRAM has two resistance states:

 The low-resistance state, which represents logical 1, and
 The high resistance state, which represents logical 0.
 Why a New Memory Controller for RRAM?

 Row-oriented versus column-oriented access mechanism

 Open-page versus closed page policies

 Refresh and restore

 PIM support
Row-oriented versus column-oriented access
mechanism
 The DRAM access mechanism is row oriented, where an access starts
with opening a memory row and reading its data to the row buffer.

 The operation is performed irrespective of whether the request type is

read or write.

 RRAM uses different system resources for different operations

 Hence, the RRAM access protocol needs to be column oriented Note

that while we propose to change what RRAM protocol should be
centered around, each row access and column
 Open-page versus closed page policies

 RRAM multiplexes multiple BLs to a single sense amplifier to reduce the cost
of the chip.

 Unlike DRAM, data from a full row are not available at the row buffer during a
read operation.

 Consequently, the RRAM memory controller can employ an open-page policy,

and closed-page policy is used.
 Refresh and restore

 Few DRAM operations, namely restore and refresh.

 RRAM because of nondestructive reads and high retention times of

RRAM.
 PIM support

 DRAM cells cannot perform PIM, the traditional memory controller

does not support PIM instructions.

 Thus, to exploit PIM capabilities of RRAM, we need to support PIM

instructions for the RRAM memory controller.
 CONCEPT DESIGN

 A memory controller is designed to perform efficient memory as well

as PIM operations in RRAM.

 The controller is divided into the front-end and the back-end We

present micro architectural modifications of transaction queues to
support new PIM instructions.

 Then, we discuss RRAM access protocol and the scheduling algorithm.

 Topics to be discussed in next presentation:

 Scheduling algorithm

 Concept front end design

 Concept back end design

 REFERENCES
 A. Pedram, S. Richardson, M. Horowitz, S. Galal, and S. Kvatinsky,
“Dark memory and accelerator-rich system optimization in the dark
silicon era,” IEEE Des.Test, vol. 39, no. 10, pp. 39–50, Apr. 2019.

 S. Kvatinsky et al., “MAGIC - Memristor-Aided loGIC, ”IEEE

Trans. Circuits Syst. II, Express Briefs, vol. 61, no. 11, pp. 895–899,
Sep. 2014.

 N. Talati, S. Gupta, P. Mane, and S. Kvatinsky, “Logic design

within memristive memories using memristoraided loGIC
(MAGIC),” IEEE Trans. Nanotechnology., vol. 15, no. 4, pp. 635–
650, Jul. 2016.
Thank you