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System Specification
HW/SW partition
ASIC
Boards Software
FPGA and
Systems
PLD
Verilog Module
Signifies declaration of a module
Name assigned to the module
Port declaration of the
Module name (ports); module
Individual statement s
within the module
endmodule
Signifies termination of a module
Port Declarations
SYNTAX
INPUT input a, b;
OUTPUT
INOUT
WIRE
REG
Identifiers
Identifiers are names given to objects so that they can
be referenced in the design.
Identifiers can start with an alpha character (a-z, A-Z)
or an underscore (_).
Identifiers contain alphanumeric, dollar signs ($), and
underscores.
Identifiers can be up to 1023 characters long.
Names of instances, modules, nets, ports, and
variables are identifiers.
Verilog is case sensitive, sel and SEL are different
identifiers.
Keywords
Keywords are special identifiers reserved to define the
language constructs.
Examples:
// Single line comment
/* Another single line comment */
/* Begins multi-line (block) comment
All text within is ignored
Line below ends multi-line comment */
Number Specification
They are of two types
Sized Numbers
Un-sized Numbers
Sized Numbers:
Syntax:<size>'<baseformat><number>
Wire a;
Reg b;
a=b; b=a;
Wire Y;
Reg A,B; Type
declaration
Syntax to declare a net
Syntax:
net_type [range] list_of_variables;
Examples:
wand w; // A scalar net of type "wand"
tri [15:0] bus; // A 16-bit three-state bus
wire [0:31] w1, w2; // Two 32-bit wires with msb = bit 0
wire #5 addr_sel; // A scalar wire with a delay
Different Types of Operators
Type of Operators Symbols
Concatenate & Replicate
Unary ! ~ & ^ ^~ |
Arithmetic * / % + -
Logical shift << >>
Relational < <= > >=
module logical_op();
reg[2:0] a,b,c;
reg x,y,z;
initia
begin
a=5,b=3’b111,c=x; Simulation
x=a&&b; result:
Y=a&&c; x=1;y=x,z=0
Z=b&&0;
$display(“x=%b,y=%b,z=%b”,xyz);
End
endmodule
Bitwise Operators
module bitwise_op();
reg[2:0] a,b,c;
AND[&]
reg x,y,z;
OR[|] initial
XOR[^] begin
NEGATION[~] a=5,b=3’b111,c=x;
XNOR[~^ or^~] x=a&b;
Y=a&c;
Z=b&1;
$display(“x=%b,y=%b,z=%b”,xyz);
end;
X= 1 0 1 endmodule
& & &
Y= 1 1 1
Simulation Result:
X=101 ,y =xxx , z=001
Z= 1 0 1
Reduction Operators
It contains only one operand and one operator,
This is unary Operator
AND[&],OR[|],XOR[^],XNOR[~^ or^~],NAND[~&]
module reduction_op();
Reg[3:0] a,b;
reg y,z;
Simulation Result: initial begin
y =1 , z=0 a=4’b0110;b=4’b1000;
Y=~&b;
Z=^a;
$display(“y=%b,z=%b”,y,z);
end
endmodule
Shift Operators
Shift Right [>>] ,Shift Left [<<]
Result is same length as operand
Logical Shift (>>,<<) module shift_op();
reg[2:0] a,b,x,y,z;
Fill the vacated bit positions with zeroes
initial begin
Arithmetic Shift Operators (<<<,>>>) a=4’b0110,b=4’b1100;
The arithmetic right shift fill the vacated x=a<<1;
bit positions with zeroes If the result Y=b>>2;
type is unsigned. Z=a>>>1;
$display(“x=%b,y=%b,z=%b”,
X,y,z);
Fill the vacated bit positions with the end
value of the MSB bit the left operand if endmodule
The result type is signed
Concatenation Operators
module concat_op();
reg a;
It is the joining together of bits Reg[2:0] b,c;
Resulting from two or more expressions Reg[7:0] x,y,z;
Operands must be sized initial begin
a=1’b1,b=3’b100;c=3’b110;
x={a,b,c};
module concat_op();
y={a,2’b01,a};
reg a;
Simulation Result: z={x[1:0],b[2:1],c};
Reg[2:0] b,c;
x= 11_100_101101 $display(“x=%b,y=%b,z=%b”,
Reg[10:0] x;
X,y,z);
initial begin
end
a=1’b1,b=3’b100;c=3’b101;
endmodule
X={2{a},b,2{c}};
$display(“x=%b”,x);
end Simulation Result:
endmodule x= 1_100_110,y=100_01_1,z=10_10_110
Relational Operators
> ,>= ,< ,<=
It evaluates to a single bit value 0(false) or
1(true)
a=4;b=3;
a=4;b=3; x=4’b1000;y=2’b11;z=4’b1x1x
x=4’b1000;y=2’b11;
x>=y //evaluates to logical 1 a<b //evaluates to logical 0
x<=y //evaluates to logical 0 a>b //evaluates to logical 1
a=4’b1x0z;b=4’b1x0z; a=4’b1x0z;b=4’b1x0z;
a==b//evaluates to x a===b//evaluates to 1
a!=b//evaluates to x a!==b//evaluates to 0
Conditional Operators
Syntax:
condition_expression ? true_expression : false_expression
reg[2:0] a,b,c,y,z;
false_exp
a=4’b1010;b=4’b0010;c=4’b1110;
out y=(&c)?a:b; //y gets b
z=c?a:b; //z gets a(c not equal to )
true_exp
condition_exp
Arithmetic operators
module arith_op();
reg[3:]a,b,c;
Multiplication[*] iteger d,e;
Division[/] reg[3:0]x,y,z;
integer k,l,m;
Substract [-] initial
begin
Add[+] a=4’b0010;b=4’b0011;c=4’b101x;
Modulus[%] d-=3; e=8;
x=a*b; //evaluates to 0110
Expensive on gates y=a+b; //evaluates to 0101
z=b-a; //evaluates to 0001
k=c*a; //evaluates to x
l=e/d //evaluates to 2,fraction is truncated
m=e%d; //evaluates to 2
end
endmodule
if else statement