Standard Cell Design and

Characterization
Dr. S. L. Pinjare
Department of ECE.
NMIT, Bangalore-560077
slpinjare@gmail.com

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 Introduction
• VLSI Design styles
• Standard Cell Design
• Characterization

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 VLSI Design Styles
• Several VLSI design styles can be considered for
implementation of specified algorithms or logic
functions.
– Full Custom Design
– Semi custom Design
• Standard-Cells Based Design
• Gate Array Design
• Field Programmable Gate Array (FPGA)

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 Standard cell vs. Full-custom IC design
• Full Custom design IC:
– Design all by yourself
– Higher performance
– Requires development of a full custom mask set
• Standard cell based IC:
– One of the most prevalent VLSI design styles
– Designed using standard cells
– Shortens the design time
– Requires development of a full custom mask set
A full custom microprocessor based on a 180 nm process
would operate at 1-2 GHz, while the same design using
Standard Cell based ASIC would operate at 200-350 MHz.

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 Standard Cell-based design
• A widely adopted design approach
in current ASIC and SOC designs.
– Standard cells come from library
provider/Vendor/FAB
– Many different choices for cell size,
delay, power dissipation
– Promotes design reuse to lower the
cost
– induces fewer errors in the design Example: Four bit 8
process operand ripple carry
Adder
– Easier to migrate
– Many EDA tools to automate the
design flow
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 Standard Cell based Design
• A Standard Cell library is a collection of basic building
blocks(Stnadard Cells) that can be used in cell-based design

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 Standard cell based VLSI design flow
Front end System specification and architecture
Functional Verification
using by Logic simulation Behavioral Description of the design
eg. NCSIM using Verilog/VHDL

Static timing analysis Synthesis of the Design (need synthesis

library) (Output: Verilog Netlist)
Back end
Floorplanning and Placement and Routing
Static timing analysis (Cadence Place and Route Tool)

Functional Verification by Layout Verification DRC, ERC,

Logic simulation eg. NCSIM Antenna rule check, LVS
or Formal Verification
Generate GDSII
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 Standard Cell Library Development Flow
Specification
Design New Meet
Layout Specification
Design New
Schematic
Cell Layout
Abstract Generation
Generate
Simulation
Model DRC/LVS
Symbol
Genration
Simulation Parasitic
Extraction Verilog /VHDL
Generation
Select best Cell
Dimensions Characterization Standard Cell Library
Generation
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 Motivation
• Standard cell libraries
– Required by almost all CAD tools for chip design
• Commercial cell libraries
– Proprietary information of the suppliers who usually impose
restrictions on the access and use of their library cells.
– Restrictions on commercial library cells hamper VLSI
research and teaching activities of academia.
• Development of a cell library is laborious process, prone
to errors and even a small error in a library cell can
possibly be disastrous due to repeated use of the cell in a
design

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 Open Source Standard Cell Libraries

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 Front-End Design Flow
• Example: a C

System c = !a & b
Specification

RTL Coding
INV (.in(a), .out(a_inv));
AND (.in1 (a_inv), .in2(b), .out(c));
Synthesis

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 Back End Design Flow

Gate Level Final Layout DRC

Place
Verilog
and
From
Route
Synthesis

Gate Level LVS

Verilog

Gate Level Dynamic/Static Analysis

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 Front End
• Gate level Net list (.v)
• Geometry Information (.lef)
• Timing information (.lib)

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 A Standard Cell library
• A collection of basic building blocks used in cell-based
design.
– Commonly used logic cells
• Characterization
– delay time vs load capacitance
– circuit simulation model
– timing simulation model
– fault simulation model
– cell data for place-and-route
– mask data

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 Cell information required
• Circuit • Timing, Power,
– Schematics, netlists functionality, and
– Layouts, parasitic operating conditions
extracted netlists – Standard industry file
– Virtuoso, format,
Caliber(Mentor)
• Synopsys Liberty format
• Abstract views (.lib file ).
– Used by Synthesis tool
– Bounding dimensions of and P&R tool.
the cell, routing
obstructions and pin • Verilog/VHDL models
locations.
• Required by the Place and
Route (P&R) tool.
– Abstract generator (LEF)
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 A Good Standard Cell Library
• Cell libraries determine the overall performance of the
synthesized logic.
• Synthesis engines rely on a number of factors for
optimization.
• Cell library should be designed to cater solely towards
the synthesis approach
– Performance, area , power optimization
– Timing, area and power reports

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 Standard cell Libraries
• Primitive cells required for digital design.
– inverters, NAND gates, NOR gates, D-latches, and flip-flops.
– More complex cells can also be included.
– Complex AOI, OAI gates, Full Adder
• Over few hundred cells

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 • Cells with wide range of drive strengths in order to support the
synthesizer and P&R tool in the optimal buffering of large nets.
– Each gate type can have multiple implementations to provide adequate
driving capability for different fanouts and fanins.
• Cells with balanced rise and fall delays (for clock tree
buffers/gated clocks)
• Larger varieties of drive strengths for inverters and buffers.
– Same logical function and its inversion as separate outputs, within same
cell

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 • Variety of flip-flops
– both positive and negative edge triggered.
– Single or Multiple outputs available for each flip-flop
• Q only, or Qbar only or both
– Different inputs for Set and Reset
• Set only, Reset only, both
– Preferably with multiple drive strengths.
• Variety of latches
– both positive and negative level sensitive.
• Several delay cells
– Useful for fixing hold time violations.
• Scan FlipFlops
– To enable scan testing of the designs,

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 Typical Cells in a Library
• Combinational Logic Cells • Sequential Logic Cells
– Buffer 1,2,4,8
eg. BUF_X1, BUF_X2,
• Latches:
BUF_4, BUF_8 – LATCH 1, 2, 4 Active
– Inverter 1, 2, 4, 8 High D latch
– NOR2, NOR3,NOR4,
1,2,4,8 – LATCH_RN 1, 2, 4
• eg NOR2_X1 Active High D latch with
– NAND2, NAND3, NAND4, asynchronous low-active
1,2,4,8
reset
– XOR2, XNOR2 , 1,2,4,8
– MUX2, MUX3, MUX4, – LATCH_RN_SN 1,2,4
1,2,4,8 Active High D latch with
– Tristate_buffer, asynchronous low-active
Tristate_inverter
reset and asynchronous
– Full_adder_1bit,
high-active set.
– Clock_driver 8,12,16,32
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 • Rising Edge triggered D-
flipflop
– DFF 1,2, 4,8
– DFF_RN 1, 2, 4,8
(Asynchronous active-low
reset)
– DFF_RN_S 1, 2, 4,8
(Asynchronous active-low
reset and Active High-set)
– DFF_QB, DFF_QB_RN ,
DFF_QB_RN_S
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• Scan Flipflops
– DFF_S_SCAN Rising-
edge triggered D flip-flop
with asynchronous active
high set input and serial
scan input.
– DFF_RN_S_SCAN
• JK Flipflop
– JKFF_QB_RN Rising-
edge triggered with
asynchronous active-low
reset and extra inverted
output
21
 • Others:
• Filler Cells
– Filler_0,
– empty cell with power and
ground rails and nwell
– Filler_1 with decoupling
capacitor
– ROW_END Cell
– Power Cells

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 Standard Cell Library Formats
• For Cadence tools: similar information is required for
other tool suites.
– Logical View (Verilog/VHDL description .v)
• Verilog is required for dynamic simulation.
• Verilog description should preferably support back
annotation of timing information. •
• Place and route tools usually can use TLF.
• Physical Layout (gdsII, Virtuoso Layout Editor)
• Abstract View (Cadence Abstract Generator, LEF) LEF:
– Contains information about each cell as well as technology
information •

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 • Timing, power and parasitics (TLF or LIB)
– Transistor and interconnect parasitics are extracted using Cadence or other
extraction tools.
– Spice or Spectre netlist is generated and detailed timing simulations are
performed.
– Power information can also be generated during these simulations.
– Data is formatted into a TLF or LIB file including process, temperature and
supply voltage variations.
– Logical information for each cell is also contained in this file.

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 • .lib/.db - Synopsys "liberty" file for Design Compiler.
– This contains information about the logic function, timing,
and power of all the cells in your library.
– The db file is just a compiled (binary) version.
• .lef - Cadence Library Exchange Format for Encounter.
– This contains the geometric information about your library
cells such as pin locations/layers, boundary, and routing
blockages.
• .tlf - Timing Library Format for Encounter.
– This contains the timing information of the library cells.

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 Standard Cell based design

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 Standard Cell Layout
• The standardized layout system enables
– automated wiring
– guarantees overall placement of standard cells, by aligning
everything on a standard grid.
• The cells are designed uniformly, watching grid
alignment and design rules,
– an automated tool reign over placement and wiring. The
circuit will be built correctly.

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 A typical Standard Cell Layout

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 Standard Cell Layout
• Routing Grids
– Both vertical and horizontal routing grids need
to be defined
• HVH or VHV routing is defined for
alternating metals layers.
– Grids are defined wrt the cell origin
– Grids can be offset from the origin, however by
exactly half the grid spacing.

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 Standard Cell Layout-Grid
• The cell height must be a multiple of the
horizontal grid spacing.
– All cells must have the same height
– Some complex cells can be designed with
double height. Eg
• High drive strength buffers
• Transistors are folded, drawn as multifingers
• The cell width must be a multiple of the
vertical grid spacing.
– However, limited routing tracks are the
bottleneck even with wider cells.

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 Standard Cell Layout
• All standard cell pins should ideally be placed on
intersection of horizontal and vertical routing grids.
– Exceptions are abutment type pins (VDD and GND)
• Routing grids are used by the CAD tools to route wires
over the standard cells placed in the design.
– Some CAD tools can route off grid, however most are optimal
when they route on grid

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 Routing Grid Spacing

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 • The values are obtained based on how close two identical wires
can be placed while, accommodating via to via switching between
horizontal and vertical layers and minimum area for each metal
layer without creating DRC errors.
– Minimum contact width and contact spacing rule
• M1 width 3 
• M2 width 3 
• Contact Spacing 3 
• Contact Width 4 
• Typically 7

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 Standard Cell Template
• We need to design and generate a template cell which
will be used for layout of all cells.
• We need to fix
– Cell height,
– Power supply line width( which metal layer –m1 or m2)
– Cell width multiple. Horizontal and Vertical grid
– nwell height,

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 • 180 nm technology
• = .1 micron
• Height =12X7 = 84 
• Width =4X 7 = 28 
• Body contacts are Placed on the
Power Supply lines
• Nwell height is 5.5 * 7 = 38.5 
• Metal1 forms power/ground rails
– 10 

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 • The width of the metal1 layer is fixed
to 10
• N-implant layer in power rail is 8
wide
• The contacts are placed at origin
sharing adjacent cells when placed.
• Contact size 2X2(0.2um by 0.2um )
• Contact Spacing : 4

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 • The minimum distance between metal1
path and poly path is 1.
• Poly extends to exactly 2 from
active(implant) region.
• Other layers are decided based on the
design rules
– Metal enclosure to contact 1
– Oxide Enclosure to contact 2
– Nimplant or pimplant enclosure to oxide 2
– Well to nwell-nimplant spacing 3
– Nimplant to Nimplant spacing 4
– Minimum Metal width 3
– Minumum Poly width .18 micron
– Power ground lines 1 micron
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 • Always make sure the metal path
layer is centered on grid line
– Metal1 and metal2 routing paths
should be centered on grid lines.
– Metal2 is always horizontal.
– Metal1 is vertical except for power
and ground rails.

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 • Pins must be centered at
grid intersection point.
– Always place a connection
or routing to another layer
at grid intersections.
– Run DRC on the cell often
to make sure no errors are
added.

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 Pin Naming Convention
• Label can be inserted for VDD
VSS Signal in and signal out
using metal 1 layer
• Place the label within the
boundary of the cell. Do not
place vdd and vss at the
boundary exactly, but inside.
• No labels should cross the cell‘s
height and width boundaries.

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 N well
• Contiguous N-Well:
– The N-well spacing is a large value
than the transistor spacing.
– If each cell has its own well, they
have to be separated by a greater
distance
– If all the cells in a row have a
common N-well, then the cells can
be placed such that it just satisfies
the transistor spacing rule leading to
greater circuit density.

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 Half-design rule
• All the layers should be set at
specific distances from the cell
boundaries by at least half the
minimum spacing rule between
them.
• violet box
– represents the cell boundary (the P&R
tool abuts these boundaries when placing
two cells side by side) and
• cyan box
– represents the boundary beyond which
no internal layers of the cell may exist.
– Minimum spacing rule for active layer

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 Typical Cell name
• AND3_X4
– 3 input And Gate with a drive strength of 4
• Synthesis of a design results in large nets and also high
fanout.
• Need high drive strength to sustain maximum clock speed.
• This also happens as the Place and route tool wires in
the standard cells.
– A 2X cell drives twice the load driven by 1X cell, a 4X twice
that of a 2X and so on. The 1X load is the load presented by
the minimum sized inverter in the cell library.

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 Inverter Cell Schematic
INV_X1
The transistor Sizes 180nm Technology
=100 nm;

PMOS W=1.400e-06 L=0.180e-06

NMOS W=0.600e-06 L=0.180e-06

45 nm technology
=25nm;

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 Circuit netlist Inverter (Schematic)
• Schematic netlist
– contains the net connections, width and length parameters of
the transistors

.SUBCKT INVX1 A Y gnd vdd

MM0 Y A vdd vdd PMOS_VTL W=1.4e-06 L=.18e-06
MM1 Y A gnd gnd NMOS_VTL W=0.6e-06 L=.18e-06
.ENDS

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 layout
• layout netlist
– includes net connections, width and
length parameters of the transistors as
well as the source and drain diffusion
areas and perimeters
.SUBCKT INVX1 A GND VDD Y
MM1 N_Y_MM1_d N_A_MM1_g N_GND_MM1_s
GND__2 NMOS_VTL L=.18e-06 W=0.6e-06 +
AD=2.625e-14 AS=2.625e-14 PD=7.1e-07 PS=7.1e-07
MM0 N_Y_MM0_d N_A_MM0_g N_VDD_MM0_s
N_VDD_MM0_b PMOS_VTL L=.18e-06 W=1.4e-06 +
AD=5.25e-14 AS=5.25e-14 PD=1.21e-06 PS=1.21e-06
.ends

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 Netlist with parasitic information Inverter
(Layout)
• have details of interconnect resistances and capacitances
– "INVX1.pex netlist.pex", "INVX1.pex.netlist.INVX1.pxi“

.SUBCKT INVX1 A GND VDD Y

MM1 N_Y_MM1_d N_A_MM1_g N_GND_MM1_s GND__2 NMOS_VTL
L=1.8e-07 W=6e-07 + AD=2.625e-14 AS=2.625e-14 PD=7.1e-07
PS=7.1e-07
MM0 N_Y_MM0_d N_A_MM0_g N_VDD_MM0_s N_VDD_MM0_b
PMOS_VTL L=1.8e-07 W=1.4e-06 + AD=5.25e-14 AS=5.25e-14
PD=1.21e-06 PS=1.21e-06
.include "INVX1.pex.netlist.INVX1.pxi"
.include "INVX1.pex.netlist.pex"
.ends
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 • The netlists are used for the following purposes:
– Schematic netlist - LVS.
– Layout netlist - Timing extraction.

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 Abstract View
• The abstract view of a cell contains
– the bounding dimensions of the cell,
– routing obstructions and
– pin locations.
• These are required for placing and
routing of the final chip by the Place
and Route (P&R) tool
• Cadence Abstract Generator tool is
used for producing the abstract view
from your standard cell layout view

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 Filler Cell
• After the final optimization phase during the place and route,
there are gaps left out between the cells in different rows.
• These gaps will cause DRC errors. To avoid them and make the
N-well continuous the gaps are filled with the FILLER CELLs.

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 A minimum dimension filler cell
• Filler0 :
– It has no active devices
– Has only power rails and an N-well.
– Usually there are a number of such cells in
the library whose widths are multiples of a
unit grid width.
– With this approach, the n-well should be at
least extended to the cell boundaries in all
the standard cells to get a clean chip after
place and route.
• As a safety measure, it might be extended a little
beyond the cell boundary.

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 Decap Cell
• Filler_n:These cells act as decoupling capacitors.
• The decoupling capacitors prevent the sagging of power supply in
the event of drawing large currents from the power rails.
– Simultaneous switching of signals specially in DFF.

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 Standard Cell Characterization
• We need various description of the cell for different
aspect of the VLSI design.
• The process of obtaining these description is called
standard cell characterization. These descriptions
collectively form the standard cell library.
• Characterization process:
– Logic function performed by each cell.
• Eg. VHDL/VERILOG description along with
– Load, each cell input will present to a signal connecting to it.
– the rise time, fall time and propagation delays, etc. for each
cell for multiple circuit conditions of loading and input slews .
– Power consumed by the cell.
– .
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 • Cell Characterization can be completed by
– analog simulation using Spectre/HSPICE simulator,
• Whose output can be evaluated to generate the timing
characterization data
– using an automated tool (Encounter library characterizer-ELC)
to tabulate this data.
• Automated tool like ELC makes the process clean, easy
and error free.
– Uses an analog simulator to simulate the design
– automates the process and give the results in the standard
Synopsys liberty file format.

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 ELC
• ELC performs a series of operations to complete the
characterization:
– Accepts input parameters such as the supply voltage, temperature, input
slew rates, output loads and process corners from the setup file.
– Analyzes the cell netlists
• Determines the logic function and the type of logic used
– Determines electrical specifications
• pin-to-pin delay, setup and hold-time constraints, pin direction are
defined for the combinational and sequential cells.
– Invokes analog simulator(Spectre or HSPICE)
• The timing, power and logic results are summarized and delays
tabulated.
– The characterized data is obtained in advanced library format (*.alf)
• Can be converted into any of the formats eg .db or .lib. The liberty file
format is a often used standard and recognized by many CAD tools.
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 Process Corner definitions
• All the standard cells are in general characterized for 3
sets of conditions:
– best case, worst case and the typical case.

• The operating conditions of a transistor affect the

propagation delays.
– The temperature affects the parameters like threshold voltage,
mobility of electrons and holes.
– The transistor thus runs faster or slower.

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 • We have to characterize at different conditions because
– the temperature and vdd on a chip vary
• from day to day and with different applications
• with die to die
• May not be uniform throughout the die.
• The chip has to function, unaffected by these slight
variations.
– If we have the timing information under different conditions,
the synthesizer can synthesize the design that can meet the
timing across the corners.

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 • The best case is when both the PMOS and NMOS
transistors run faster than usual
– higher power supply (typically +10% more than nominal) and
Lowest expected operating temperature.
• The worst case is when both transistors are slow
– Higher expected temperature and lower supply voltage (-10%
usually).
• Typical case is at the room temperature when both the
transistors are typical and the nominal VDD.

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 Device model file
• The device models come with the given
ProcessDesignKit and consist of both passive and active
device models.
– Transistor models- defines various parameters such as the
threshold, per unit capacitances, resistances, oxide thickness,
etc.
• we must have the transistor models for all Process
Corners
– slow-n slow-p, slow-p fast-n, fast-p fast-n, typical-n typical-p
etc

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 Intrinsic delay and input slew
• The intrinsic delay is the inherent parasitic delay
exhibited by a logic gate for the transistors to turn
ON/OFF.
• The transistor currents cannot switch faster than this.

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 Input slew rate calculation.
• The input slew is the rise/fall time of the input.
– Usually the output of a gate is connected to input of another,
and hence when we are characterizing the logic gate
individually it should not be given inputs that rise/fall faster
than the intrinsic delay. This should be considered, while
setting up the input slew.

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 Output net Capacitance
• The capacitance on the output node also contributes to
the delay.
• Hence the cells are characterized for different loads to
get the timing
• The 1X load is determined using the minimum sized
inverter (INVX1) of the cell library

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 • The characterization data is output in the form of a matrix with
the input slew on one axis and the output load on the other axis
• Setup for two input nor gate
Index X1{
Slew = 0.025n 0.05n 0.075n 0.1n 0.125n;
Load = 0.05f 1f 2f 4f 8f; };
Index X2{
Slew = 0.025n 0.05n 0.075n 0.1n 0.125n;
Load = 0.05f 2f 4f 8f 16f; };
Index X4{ Slew = 0.025n 0.05n 0.075n 0.1n 0.125n;
Load = 0.05f 4f 8f 16 32f ; };
• The 0.05 fF in the load index is to obtain the parasitic delays of
the gates.
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 Delay as a Function of load capacitance for
different Slew rate

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 Timing characterization data for NOR3X1 gate
• Propagation delays (rounded to 3 decimal places) obtained for a
NOR3X1 gate for different input rise/fall times (Ts) and loads
(CL).

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 • The parasitic delays (y-
intercept)
– 22 pS for input slew rate of 15
pS is
• Increases with input slew
rates. Delay =gh+p
– Due increase in leakage current
with increasing input slope
• The effort delays increase – The slope of the lines (g)
linearly with the increase in gives the logical effort.
output load that has to be • Constant for a given gate
independent of loads/input
driven. slew rates
– agrees with the theoretical
value (7/3 = 2.33).

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 Characterizing pin to pin delay
• Propagation Delay: Time to affect a change at the output
pin, given that a change at the input pin takes place .
– Vth is the threshold voltage level at which the delay is
measured and is defined as half of logic high value or VDD/2.

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 Characterizing set up and hold times
• When characterizing a sequential cell, the timing
constraints have to be met for the data to propagate
correctly through it.

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 Set up time/Hold time calculation
• Binary Search:
– Two initial values of Set up time for which the simulation
passes and fails respectively are given in the setup file.
– The simulation is done by allowing the data to change with
respect to clock at the midpoint of these two values.
– If it passes then the pass set up time value is updated or else
the fail time is updated, and the iterations are continued until
the specified resolution is obtained.
• The resolution determines when to quit the algorithm. The resolution is
chosen to be equal to the intrinsic delay of the fastest gate in the library
– Similarly the hold time is also determined.

Bisec 6n -6n 0.1 n

Setup time max 6n setup time min -6n
resolution time 0.1 ns
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 derating factors
• The parasitics are obtained from layout but this
information must be estimated when no layout
information is available.
• Also it is not possible to predict the process, voltage and
temperature variations
• derating factors can be included to compensate for these
variations

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 Summary
• Tasks to be carried out in development of a cell Library
– Layout generation_GDS_II
– Physical verification
– netlist extraction
– cell characterization, and
– generation of Synopsys Liberty Format file
• Design automation using
• Skill, Tcl, Perl and Shell script

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 • IIT/OSU standard cell
library 2-XOR gate in
0.18µm technology
showing lots of metal-2
crossovers.

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 D-Flipflop with set reset inputs

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 Thank You

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 LEF Library Exchange Format
• An ASCII File
– Includes the design rules for routing and the Abstract of the
cells
– No information about the internal netlist of the cells

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 • A LEF file contains the following sections:
– Technology: layer, design rules, via definitions, metal
capacitance „
– Site: Site extension „
– Macros: cell descriptions, cell dimensions, layout of pins and
blockages, capacitances.
• The technology is described by the Layer and Via statements.
– To each layer the following attributes may be associated:
• type: Layer type can be routing, cut (contact), masterslice (poly,
active), overlap. „
• width/pitch/spacing rules, „
• direction „
• resistance and capacitance per unit square „
• antenna Factor
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 • TLF is an ASCII file
– The timing and power parameters associated with any cell in a
particular semiconductor technology .

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 Timing Library Format
TLF
• The timing and power parameters
– Obtained by simulating the cells under a variety of conditions.
• Timing models and data to calculate
– I/O delay paths
– Timing check values
– Interconnect delays.
• I/O path delays and timing check values are computed on a per-
instance basis
• Path delays in a circuit depend upon the electrical behavior of
interconnects between cells

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 • .tcl/.scr - TCL scripts that could be for Design Compiler,
Encounter, or Primetime.
• .v/.mapped.v - The unsynthesized and synthesized (gate-level)
netlist, respectively.
• .io - A proprietary file for Encounter that specifies which IO pads
should be used for which IOs on your top module.
• .sdc - Synopsys Design Constraints. This is a file that contains the
definitions of your clocks, input/output delays and other design
constraint information to pass between tools. Synopsys saves this
file after you set up the constraints and Encounter/Primetime can
read the file later so that the same constraints are used.

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