Organizing Engineering

Research Papers (16)

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Computer architectures simplify complex arithmetic
operations using a float-point process unit (FPU).
While many FPUs adopt a divider to achieve high-
speed arithmetic operations, conventional dividers expend
numerous basic arithmetic operations, including addition,
subtraction and generation of a quotient. The execution time
and power dissipation of a divider positively correlate with the
number of basic operations, explaining why this divider
consumes much time and power.
For instance, a conventional divider requires
m/2 additions, m subtractions and m shifts to produce the m-bit
quotient. The time-consuming feature limits clock speed of the
embedded divider.
Portable devices have difficulty in using the
conventional divider owing to high-power dissipation,
necessitating the development of a high-speed and low-power
divider.
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Based on the above, we should develop a high-speed and
low-power divider.
To do so, the iterations of generating a quotient can
be significantly reduced by a high-radix arithmetic system. The
operations of addition can then be eliminated with a non-restoring
algorithm. Next, the power dissipation can be diminished via a domino
logic circuit.
As anticipated, the proposed divider using a high-radix
arithmetic system and a non-restoring algorithm is 35% faster than
conventional dividers. Moreover, the divider based on a domino logic
circuit can decrease power dissipation by 15%.
Furthermore, in addition to providing further insight into
developing a high-speed and low-power divider, the proposed scheme
can be easily implemented in portable devices owing to its low-power
consumption.
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Wireless communications is increasingly popular, especially
in mobile phone and USB dongle card applications. The antenna of
these devices is arranged on the edge of a ground plane in a wireless
system, making the antenna radiation patterns asymmetrical and the
peak radiation power moving towards the system ground. For instance,
in mobile phones, the human hand absorbs peak radiation power,
subsequently degrading communication quality and shortening the
range of communication.
However, an increased power consumption reduces usable
time of mobile phones. For wireless devices, the peak radiation power
is located at *** and the antenna gain at *** plane is lower than O dBi.
Additionally, radiation power of 50% in a human hand
makes the communication distance only half that of the theoretical
value, which is estimated in free space.
Asymmetrical characteristics of the patterns consume
an excessive amount of power, thus degrading the performance of
wireless communications.
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Based on the above, we should develop a
control technology method for radiation patterns.
To do so, the pattern direction can be
adjusted using an additional metal reflector from
conventional patterns. However, this method increases the
system size, which is inappropriate for portable device
applications. Asymmetry of the antenna radiation patterns
originates from various current distributions on the system
ground plane and the antenna. Thus, cancelling the
ground plane current can avert destructive interference in
the far field. Next, out of phase ground plane current can
be changed to be in the phase current to produce
interference in the far field. Additionally, RF clock can be
placed into the system to filter out the phase current.
Moreover, contracting the ground plane size can be
adopted to avoid an unnecessary ground current.
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As anticipated, the proposed method
can alter the location of the peak radiation power
from *** to ***. Meanwhile, the antenna gain at ***
can reach 0.5 dBi.
This modification can increase the
communication distance, lower power
consumption, and enhance communication quality.
Further details can be found at
http://www.chineseowl.idv.tw