Documente Academic
Documente Profesional
Documente Cultură
Dedicated to Z. Haghshenas
Introduction
2
DSPs Features
3
DSPs General Applications
5
DSPs Characteristics
6
Data Path
DSPs GPPs
Performs all key arithmetic Multiplies often take >1
operations in 1 cycle. cycle
Hardware support for Shifts often take >1 cycle
managing numeric fidelity: Other operations (e.g.
Shifters saturation, rounding)
Guard bits typically take multiple
Saturation cycles
7
DSPs Data Path Example
A representative conventional
fixed-point DSP processor data
path (from the Motorola
DSP560xx, a 24-bit, fixed point
processor family)
8
Instruction Set
DSPs GPPs
Specialized, complex General-purpose
instructions instructions
Multiple operations per Typically only one
instruction (e.g. using operation per instruction
VLIW)
9
VLIW
DSPs GPPs
Harvard architecture Von Neumann architecture
2-4 memory accesses/cycle Typically 1 access/cycle
No caches—on-chip May use caches
SRAM
11
Von Neumann Architecture
12
Harvard Architecture
13
Addressing Modes
DSPs GPPs
Dedicated address Often, no separate address
generation units generation unit
Specialized addressing General-purpose
modes; e.g.: addressing modes
Auto-increment
Modulo (circular)
Bit-reversed (for FFT)
Good immediate data
support
14
Execution Control
15
Peripherals
Host ports
Bit I/O ports
On-chip DMA controller
Clock generators
Synchronous serial ports
Parallel ports
Timers
On-chip A/D, D/A converters
16
DSPs classifications (1)
By arithmetic format
Fixed-point
Floating-point
Block floating-point
By data width
Typical fixed-point DSPs: 16-bit
Typical floating-point DSPs: 32-bit
By memory organization
By multiprocessor support
17
DSPs classifications (2)
By speed
Million of instruction per second (MIPS)
A basic operation (e.g. MAC)
A basic algorithm (e.g. FFT, FIR or IIR filter)
Benchmark programs
By power consumption
Operating voltage
Sleep or idle mode
Programmable clock dividers
Peripheral control
18
DSPs Evolution
19
First Generation (1982)
16-bit fixed-point
Harvard architecture
Accumulator
Specialized instruction set
390 ns MAC time (228 ns
today)
20
Second Generation (1987)
21
Third Generation (1995)
23
DSPs Evolution Chart
24
DSPs Performance Chart
25
Role of GPPs (1)
Added capabilities:
Add single-instruction, multiple-data instruction set
extensions (e.g., MMX Pentium)
Integrate a fixed-point DSP processor-like data path and
related resources with an existing mC/mP core (e.g. Hitachi
SH-DSP)
Add a DSP co-processor to an existing mC/mP core (e.g.,
ARM Piccolo)
Create an all-new, hybrid architecture (e.g. Siemens TriCore)
26
Role of GPPs (2)
Assisted capabilities:
Very high clock rates (500-1000 MHz)
Super scalar (“multi-issue”) architectures
Single-cycle multiplication and arithmetic ops.
Good memory bandwidth
Branch prediction
In some cases, single-instruction, multiple-data (SIMD)
ops
Caching & pipelining
27
Conclusion
28
Web Links & Information
http://www.bdti.com
http://www.eg3.com/dsp