8085

Microprocessor
Machine Cycles

Dayanand K
 8085

UNIT 1 BASIC CONCEPTS 9 Hrs.

8085 Microprocessor - Architecture and its operation, Concept of instruction
execution and timing diagrams, fundamentals of memory interface -
Addressing modes
 8085

Fundamentals of Memory Interface

 8085

Memory interface
INTEL 8085 can be interfaced with Max of 64KB Memory Unit
It may be RAM and ROM of 32 KB each symmetrically or
asymmetrically.
• The memory unit has address decoder, multiplexer,
Output/input buffer, and memory location etc.
• Decoder Decodes the address and locks the appropriate one.
• Multiplexer chooses the location and connects it with data bus.
• Output buffer works in the case of Read operation and input buffer
in the case of write operation. Output buffer sends the data to Data
bus and Input buffer receives the data from data bus.
• For ROM input buffer is disabled.
 Memory Unit 8085

Chip select- CS’

Address Latch Enable-

ALE

ADDRESS DECODER
64KB
Location
Address bus (16 Bit) Capacity
8 Bit = 1 Byte/Location or
Address
A0-A15 address
(0000 to FFFF)

Read-RD’
Write-WR’

MUX

Output

Input
Input
Data Bus (8 Bit) - D0-D7
 8085

Memory Interfacing
ALE

A8-A15 (HIGHER ADDRESS BUS)

AD0-AD7 (LOWER
ADDRESS AND ADDRESS
ADDRESS BUS (A0-A7)
DATA BUS) LATCH

8085 MEMORY
DATA BUS (D0-D7)

IO/M’ CS’

RD’
WR’

S1 S0
 8085

Signals used in Memory Interface

• IO/M’, RD’, WR’ are the signals (ACTIVE LOW) from Processor and CS’ is
the Chip select pin of Memory Unit.
• Bus Signals are
• Address Bus Signals- A0- A15 and
• Data Bus Signals D0-D7
• IO/M’ should be connected to CS’ and be Low(=‘0’) for Memory to be
enabled
• RD’ shall be Low(=‘0’) for READ operation-OUTPUT Buffer Shall be
connected to Data bus
• WR’ shall be Low(=‘0’) for WRITE operation-INPUT Buffer Shall be
connected to Data bus

• ALE signal Enables ADDRESS BUS(A0-A15) if HIGH(=‘1’) and DATA BUS

(D0-D7) if LOW(=‘0’).
• If ALE is LOW then only READ and WRITE operation can be done.
 8085

Concept of Instruction Execution

 Machine Cycle 8085

Status and Control Signlas

IO/M’ S1 S0 RD’ WR’ OPERATION MACHINE CYCLE
Z X X Z Z HOLD HOLD
Z 0 0 Z Z HALT HALT
0 1 0 1 1 IDLE BUS IDLE
0 0 1 0 1 MEMRD’ MEMORY READ
0 1 0 1 0 MEMWR’ MEMORY WRITE
0 1 1 1 1 FETCH OPCODE FETCH
1 0 1 0 1 IORD’ INPUT OUTPUT READ
1 1 0 1 0 IOWR’ INPUT OUTPUT WRITE
1 1 1 1 1 INTA INTERRUPT ACKNOWLEDGE

Z-HIGH IMPEDANCE STATE

X-INDETERMINATE STATE
 8085

Opcode Fetch Machine Cycle

ALE Opcode Fetch
1
0
A8-A15 (HIGHER ADDRESS BUS)
MEMORY
HIGHER 8- LOWER 8-
BIT ADDR BIT ADDR OPCODE
AD0-AD7 (LOWER ADDRESS AND DATA
BUS)
16 BIT ADDRESS

8085 IO/M’
0
1
INPUT OUTPUT
RD’ 0
1 DEVICES

WR’ 0
1

0 S1
1 S0 0
1
 8085

Memory Read Machine Cycle

ALE MEMORY READ
1
0
A8-A15 (HIGHER ADDRESS BUS)
MEMORY
HIGHER 8- LOWER 8-
BIT ADDR BIT ADDR 8 BIT DATA
AD0-AD7 (LOWER ADDRESS AND DATA
BUS)
16 BIT ADDRESS

8085 IO/M’
0
1
INPUT OUTPUT
RD’ 0
1 DEVICES

WR’ 0
1

0 S1
1 S0 0
1
 8085

Memory Write Machine Cycle

ALE MEMORY WRITE
1
0
A8-A15 (HIGHER ADDRESS BUS)
MEMORY
HIGHER 8- LOWER 8-
BIT ADDR BIT ADDR
8 BIT DATA
AD0-AD7 (LOWER ADDRESS AND DATA
BUS)
16 BIT ADDRESS

8085 IO/M’
0
1
INPUT OUTPUT
RD’ 0
1 DEVICES

WR’ 0
1

0 S1
1 S0 0
1
 8085

IO Read Machine Cycle

ALE IO READ
1
0
A8-A15 (HIGHER ADDRESS BUS)
MEMORY
LOWER 8-
BIT ADDR
AD0-AD7 (LOWER ADDRESS AND DATA
BUS)
8 BIT ADDRESS

8085 IO/M’
0
1
INPUT OUTPUT
8 BIT DATA
RD’ 0
1 DEVICES

WR’ 0
1

0 S1
1 S0 0
1
 8085

IO Write Machine Cycle

ALE IO WRITE
1
0
A8-A15 (HIGHER ADDRESS BUS)
MEMORY
LOWER 8-
BIT ADDR
AD0-AD7 (LOWER ADDRESS AND DATA
8 BIT DATA BUS)
8 BIT ADDRESS

8085 IO/M’
0
1
INPUT OUTPUT
RD’ 0
1 DEVICES

WR’ 0
1

0 S1
1 S0 0
1