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IEEE-DASC at SystemC Japan2010, 01Jul2010 2 © Copyright 2010 JEITA Copyright(C) JEITA 2008
JEITA Structure and
Management
JEITA
Japan Electronics and Information Technology Industries Association
Policy and Strategy Board
Environment Board
Consumer Electronics Board
IT and Industrial Systems Board
Display Devices Board
Electronic Components Board
Semiconductor Board (JEITA-JSIA)
Semiconductor Industrial Affairs Committee
Semiconductor International Affairs Committee
IEEE-DASC at SystemC Japan2010, 01Jul2010 3 © Copyright 2010 JEITA Copyright(C) JEITA 2008
EDA-TC Structure in Fiscal Year
2010
EDA Technical CommitteeChair: Yoshida (Renesas)
Acceleration of Standardization
EDA Standardization Technical Sub-Committee
Chair : Imai (Toshiba), Vice-chair : Kawamura (Fujitsu SL)
SystemC Working Group Kojima (NECST)
Chair : Imai (Toshiba)
LSI-Package-Board Co-design Working Group
Chair : Fukuba (Toshiba)
IEEE-DASC at SystemC Japan2010, 01Jul2010 4 © Copyright 2010 JEITA Copyright(C) JEITA 2008
EDA Standardization TSC Activities
Members: semiconductor vendors, EDA vendors and
academia
Chair: Imai (Toshiba)
Vice-chairs: Kawamura (Fujitsu SL), Kojima (NECST)
IEEE-DASC at SystemC Japan2010, 01Jul2010 5 © Copyright 2010 JEITA Copyright(C) JEITA 2008
SystemC Working Group
To standardize design language and its subsidiaries of synthesis
and verification to support ESL design methodology
Current activities:
Work with IEEE P1666-WG to contribute SystemC-2010 standards
to add TLM 2.0 features and correct SystemC-2005 errata
Execute survey on SystemC, and share the result with other regional
SystemC User Group (World-Wide). Continue the survey in SystemC
Japan 2009 and 2010 after deciding no System Design Forum in
conjunction with EDSFair2010
IEEE-DASC at SystemC Japan2010, 01Jul2010 6 © Copyright 2010 JEITA Copyright(C) JEITA 2008
LSI-PKG-Board Co-design Working Group
A new WG was formed and to aims harmonization for co-
design environment among LSI, Package and Board in April,
2010 after Fukuba-san in Toshiba and his team had intensively
discussed since summer 2009.
Member : 24 Experts from 16 Companies and academia
Chair: Fukuba (Toshiba), Vice-chair: Takana (SONY)
Fujitsu SL, SONY, Renesas, Panasonic, Toshiba, Zuken,
IEEE-DASC at SystemC Japan2010, 01Jul2010 8 © Copyright 2010 JEITA Copyright(C) JEITA 2008
Collaboration w/IEEE and IEC
Domestic collaboration
To dispatch a chair and some experts to WG2 of IEC TC93 JNC in IEICE
(The Institute of Electronics, Information and Communication Engineers)
and to lead the activities of the WG2 JNC
Global collaboration
Worked with P1800WG (SystemVerilog), P1666WG (SystemC) and
P1801WG (Power format) in IEEE-DASC, reviewing the drafts and
participating in the balloting. Planning work with P1481(SSPEF)
Has been a member of IEEE-SA since 2004 and participated in balloting
Kojima has been a Co-convener of TC93 WG2 since 2000 and worked
Equivalence check
Softwar Area
e
Logic Timing
To set strategies of EDA Communicat
Scan/BIST Power
standardization activities e
Circuit Noise
for every category
Place Libraries DFT
Route DFM
Data for
IEEE-DASC at SystemC Japan2010, 01Jul2010 11 manufacturing
© Copyright 2010 JEITA Copyright(C) JEITA 2008
Design languages harmonization
JEITA had some good lessons-learned through power format
standardization activities under 2 formats issues of UPF and CPF
Criteria to qualify De Jure standard is applicable for practical
IEEE-DASC at SystemC Japan2010, 01Jul2010 12 © Copyright 2010 JEITA Copyright(C) JEITA 2008
Bird’s-eye view for Design Languages
BVDL aims to make full use of planning and decision-making on
JEITA activities and to facilitate global understanding of various
design languages, classified into De Jure standards, Forum
standards and De Facto standards
Current status
We have created the first version of BVDL
We will use it for upcoming 2010 fiscal year planning
IEEE-DASC at SystemC Japan2010, 01Jul2010 13 © Copyright 2010 JEITA Copyright(C) JEITA 2008
How to read BVDL. Design flow
(X-axis)
The X-axis of BVDL’s chart corresponds to design flow.
The languages used in each design step of the flow are shown.
Design Flow (X-Axis)
Analog Functional Design Post-Layout Circuit
Analog Architecture Design Verification
VerilogーAMS
VHDLーAMS
SPICE
Design
FSDB
Language
SystemVerilog
SystemC
Verilog
Design
VHDL
Language
トランジスタ・
レベル回路設計
SystemVerilog
論理合成
TouchStone
IP ーXACT
RTL設計・ 検証 機能設計、アーキテクチャ設計
SystemC
Rosetta
Verilog
Liberty
GDS II
OASIS
Esterel
VHDL
BSDL
CDL
LEF
高位設計・検証
UML
設計言語
IBIS
CITI
設計言語
VerilogーAMS
Open Access
VHDLーAMS
TouchStone
VerilogーA
SystemVerilog
SystemVerilog
SPICE
GDS II
OASIS
FSDB
SystemC
CITI
Verilog
Verilog
設計言語
VHDL
FSDB
記述対象物
CPF
UPF
PSL
設計言語 IEEE # 1800 1364 1076 1685
記述対象物
e
IEEE # P1778 P1699 1666 ー 1149.1b
大分類 小分類 IEC # 62014 ー 大分類 小分類 IEC # 62530 61691ー4 62248
電子機器システム 構成 X X ライブラリ、コンポーネント・モデル
論理ライブラリ・モデル X X X
電子機器システム 論理動作・機能 X X X X X 記述対象物 IEEE # 1666 1800 1364 1076 1801 1647 1850 ー 1800 1364 記述対象物 IEEE # ー ー ー ライブラリ、コンポーネント・モデル
配置配線用ライブラリ・モデル X
大分類 小分類 IEC # ー ー ー ライブラリ、コンポーネント・モデル
レイアウトデータ X X
電子機器システム 論理動作・機能ーAMS拡張 X 大分類 小分類 IEC # 62530 61691ー4 62248 62531 ー 62530 61691ー4
SoCハードウェア 構成 X X X ライブラリ、コンポーネント・モデル
遅延計算モデル X
電子機器システム 性能・特性 X X SoCハードウェア 構成 X X X X X X
電子機器システム 性能・特性ーAMS拡張 X SoCハードウェア 論理動作・ 機能 X X LVS用ネットリスト
ライブラリ、コンポーネント・モデル X
SoCハードウェア 論理動作・ 機能 X X X X X X IP IPメタデータ X
電子機器システム 検証用記述 X X X X X SoCハードウェア ゲート様レベル回路 X X X X X SoCハードウェア 論理動作・ 機能ーAMS拡張 X X
電子機器システム 検証用記述ーAMS拡張 X SoCハードウェア タイミング制約 SoCハードウェア アナログ動作 ・機能 X X X
SoCハードウェア I/ Oバッファ特性 X SoCハードウェア 電源構造 X X SoCハードウェア ゲート・レベル回路 X X X
SoCテスト バウンダリスキャン回路 X SoCハードウェア フロアプラン SoCハードウェア トランジスタ・レベル回路 X X X X
素子特性 素子特性(パラS メータ、他) X X SoCハードウェア 配置配線データ SoCハードウェア タイミング制約
SoCハードウェア レイアウトデータ SoCハードウェア 電源構造
機能検証 テストベンチ X X X X X X X SoCハードウェア フロアプラン
機能検証 プロパティ X X X SoCハードウェア 配置配線データ X
機能検証 アサーション X X X SoCハードウェア レイアウトデータ X X
機能検証 機能カバレッジ X X X 機能検証 テストベンチ X X X
機能検証 トランザクタ X X 機能検証 テストベンチーAMS拡張 X X X
機能検証 テストパターン X X X X X 機能検証 プロパティ
機能検証 ランダム検証 X X X 機能検証 アサーション
4. Characterization,
EDA:ツール間インターフェース
論理・回路シミュレーション結果 X 機能カバレッジ
EDA:ツール間インターフェース
配線寄生容量 機能検証 トランザクタ
EDA:ツール間インターフェース
配線寄生抵抗 機能検証 テストパターン X X
EDA:ツール間インターフェース
配線を構成する端点座標 機能検証 ランダム検証
EDA:ツール間インターフェース
LVS用ネットリスト EDAツール間インターフェース論理・ 回路シミュレーション結果 X
EDA:ツール間インターフェース延時間
様 EDAツール間インターフェース配線寄生容量
SoCテスト バウンダリスキャン回路 EDAツール間インターフェース配線寄生抵抗
EDAツール間インターフェース配線を構成する端点座標
4. Characterization / IP Preparation
SoC Manufacturing
IEEE-DASC at SystemC Japan2010, 01Jul2010 16 © Copyright 2010 JEITA Copyright(C) JEITA 2008
The Four Major Design Processes
Electronic System Design
Electronic System Design is a design process to develop electronic systems.
The Electronic System Design chart of BVDL describes interface with SoC design
mainly.
This is because JEITA EDA-TC’s activity is primarily for semiconductor industry.
SoC Design
SoC Design is a design process to develop System-on-Chips.
The SoC Design chart of BVDL describes only digital part of SoC design.
This is to make the chart easy to understand.
Analog circuits are developed in the Analog Block Design process and are
imported as blocks.
This is not always true. But it is NOT worthy to create a perfect definition of total
design process for our purpose.
IEEE-DASC at SystemC Japan2010, 01Jul2010 17 © Copyright 2010 JEITA Copyright(C) JEITA 2008
The Four Major Design Processes
(cont’d)
Analog Block Design / Mixed-Signal Verification
Analog Block Design is a design process to develop analog blocks.
The blocks developed in this process are provided to the SoC design flow
through “Characterization / IP Preparation” process.
Mixed-Signal Verification is the process to verify the interface between the
digital portions and the analog portions.
Characterization / IP Preparation
“Characterization / IP Preparation” is a design process to prepare data of
analog blocks and IPs.
The prepared data in this process are provided to other design processes.
The languages for the interface data are collected, but the definitions of
this process is under discussion now.
IEEE-DASC at SystemC Japan2010, 01Jul2010 18 © Copyright 2010 JEITA Copyright(C) JEITA 2008
How to use BVDL. Example-1.
Case
Two languages exist in the same design phase and
define the same design objects.
Example: UPF and CPF
Action Candidates.
Clarify the difference of the languages.
Minimize the obstacles to keep interoperability of the
languages.
IEEE-DASC at SystemC Japan2010, 01Jul2010 19 © Copyright 2010 JEITA Copyright(C) JEITA 2008
How to use BVDL. Example-2.
Case
Technology shift from lower level to higher level.
Example: “RTL Compile” and “C Compile”
Action Candidates.
Learn from old technology and make plan for new technology.
Design Constraint
Constraint Check
(SDC, UPF)
Purpose.
For planning and decision making on our standardization
activities.
To accomplish global understanding of design languages.
Future Plan
We will put the finishing touch to our BVDL.
We will use it for the coming 2010 fiscal year planning.
IEEE-DASC at SystemC Japan2010, 01Jul2010 21 © Copyright 2010 JEITA Copyright(C) JEITA 2008
JEITA : Japan Electronics and Information Technology Industries
Association
( URL http://www.jeita.or.jp)
EDA-TC : EDA Technical Committee
( 22
URL http://eda.ics.es.osaka-
u.ac.jp/jeita/eda/index.html)