Outstanding Challenges in Testing

Nanotechnology Devices

Kewal K. Saluja
Department of Electrical and Computer Engineering
University of Wisconsin-Madison

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 1

 Cost of Integrated Circuits
Fixed cost
Cost per IC = + Variable cost per IC
volume

Fixed cost to produce the design: One time cost

 Design cost (= Design + Design Verification + Debugging)
 Test generation cost
 Fabrication cost
In-house (fabrication equipment) or external contract
Mask making, number of metal layers, technology and materials
Variable cost per IC: Recurring cost
 Assembly and packaging
 Test application cost (DFT, test equipment, test generation)
Cost of testing will EXCEED the cost of design/manufacturing

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 2

 Microprocessor Cost per Transistor:
Cost of testing will EXCEED the cost of design/manufacturing
(Source: ITR-Semiconductor, 2001)

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 3

 Test Application Cost
Test Application Cost = No. of Vectors · No. of FFs
No. of Pins · Frequency of tester
No. of Vectors ~= (No. of Gates)α, α = 0.7 ~ 0.9
No. of FFs ~= (No. of Gates)β, β = 1.0 ~ 1.0+
No. of Pins ~= (No. of Gates)γ, γ = 0.5 or less (ITRS 2001)
Frequency of tester: expected to be almost constant for each
decade (ITRS2001)
Test Application Time ~= (No. of Gates)α+β-γ, α+β-γ = 1.1 ~ 1.3
Rate of Test Application Time Change
 No. of Gates are doubled for every 18 months (Moore’s law)
 No. of Tests are doubled when No. of Gates are 1.87X or 1.70X
=> No. of Tests are doubled for every 13 to 16 months

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 4

Increase in Gate Count vs. Test Application Time
(1997-2007)
700
Gate Count (Doubles 18)

600 TAT (Doubles 13)

TAT (Doubles 16)

500

400

300

200

100

0
1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 5

 Overview of General Difficulties
Present and near future testing problems (≤2015)
 Test generation and fault simulation for traditional and non traditional
fault models for a single core
 Test generation and test application cost (test data volume)
 Reduction of test application power
 Thermal constraint testing
 Fault diagnosis for volume production
 Test generation, DFT, BIST and test application problems for
multicore ICs
Future testing problems (>2015)
 DFT and standardization challenges
 Operational life failures
 Esoteric technologies

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 6

 Signal Integrity Problems
Noise faults caused by parametric variations:
Must be properly modeled to levels of abstraction higher than the
electrical, circuit, and transistor levels for the purposes of fault
simulation, ATPG, and BIST
signal integrity verification problems are becoming test problems.

 Crosstalk-induced delay and pulses

 Distributed delay variations
 Excessive voltage drop and/or swing on power nets
 Substrate and thermal noises
 Process variations (pvt – process, voltage, temp
problems)
KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 7
 Crosstalk Faults
Coupling between nets posts a serious problem in
high-speed, deep-submicron VLSI circuits.
Two types of coupling effects
 Crosstalk-induced delay - signal transition rate of a line
altered by simultaneous transitions on other lines
Speed-up: same direction
Slow-down: opposite direction
 Crosstalk-induced pulse - transition on an “aggressor” line
induces temporary signal value change on a “victim” line
Pulse on the victim line
If victim is a clock line, spurious pulse can cause flip-flops to capture
incorrect logic values

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 8

 Crosstalk-Induced Delay

Crosstalk slow-down Crosstalk speedup

Time
victim
Victim-line Victim-line

Aggressor-line Aggressor-line

Time
aggressor

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 9

 Crosstalk-Induced Pulse

Data in

D
Data in Data out
Q

CLK
captur captur
(victim) e e

coupling

Aggresso
r

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 10

 Testing Crosstalk Faults
Large combination of aggressor-victim pairs
even in relatively small circuit
Conventional method of testing crosstalk
faults
 Determine aggressor-victim fault-pair candidates via layout
information (parasitic capacitances, locality, etc)
 Simulate each fault at electrical-level (SPICE and the like)

Limitations
 Low-level simulation very time-consuming
Coverage possibly limited by time constraint
 Inability to incorporate common fault simulation techniques
Concurrently simulating faults, fault-dropping, etc

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 11

 Crosstalk Fault Simulation

Logic-level crosstalk fault simulation potentially

requires much less computational resources and time
 More faults can be simulated

Can be integrated into conventional scheme

 Logic-level fault simulation to filter out undetectable faults
Reduce fault candidate pool to a manageable size
 Layout information, can further reduce the candidates in this pool
 Electrical-level simulation for remaining faults (as a verification)

Drastically reduce simulation time

 Same or better accuracy

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 12

 Operational-Life Faults

Certain classes of faults are hard to identify during normal

manufacturing test process
 Result of dielectric, conductor, metallization failures

Responsible for failures during a device’s operational life

 Soft (transient) faults – soft errors due to cosmic rays
 Device degradation (NBTI)
 Hard (permanent) faults

Hard faults should be detected

Devices should be able to tolerate both soft and hard
faults

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 13

 Test data volume: Output compaction

Scan design tested by Automated Test Equipment.

Inputs: Outputs:
Test stimuli Test response

r ot c ap mo C
Objectives: reduce test application time and test volume
stored on the ATE.

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 14

 Model: block compactor

Input Linear
data block compactor Output
data block

n n.d m.d
m

d
d
KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 15
 Linear compactors
Compactors implemented with xor trees.

in 1
in 2 Row of weight 3
in 3
n.d inputs in 4
in 5
in 6 Row of weight 1
in 7
in 8
out out out out
1 2 3 4

m.d outputs
KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 16
 Single weight compactors

Construction: every row is non-zero, different

and with identical, odd weight.
Property in the 1
1
absence of X values: 0
0
One, two, or any odd
0
number of errors are 0
0
guaranteed to be
0
detected.
0 1 0 1 0

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 17

 Main idea
Observation: X values are non-uniformly
distributed among the scan chains.
100
Example:
Percentage of Xs

80 microprocessor with
60 150K scan cells.
40 s=10
s=1: 40 scan chains.
s=4
20 s=4: 160 scan chains.
s=1 s=10: 400 scan chains.
0
0 10 20 30 40 50
Percentage of scan chains
KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 18
 Main idea
Observation: X values are non-uniformly
distributed among the scan chains.
Modified scheme:
 Use matrices with multiple weights.
 Assign:
Low weight to scan chains producing many Xs.
High weight to scan chains producing few Xs.

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 19

 Multiple weight compactors

Construction: every row is non-zero, different and with

odd weight.
Property in the
1
absence of X values:
1
Same as single weight. 0
One, two, or any odd 0
0
number of errors are
0
guaranteed to be 1
detected. 0

0 0 0 1 0

KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 20

 Introduction: Test Scheduling
BIST

Core 1 Core 2 BIST Core 3

External
Test Bus

Core 4 BIST Core 5 Core 6

BIST

Test Scheduling: In order to reduce the test cost, the testing

time must be minimized by carefully scheduling tests for cores at
the system level and the tests must be scheduled without violating
any constraint.
 Background: History
Iyengar and Chakrabarty ‘02

Bild, Dick etc. ‘08

Craig, Kime and Saluja ‘88

Kime and Saluja ‘82 Rosinger and Al-Hashimi ‘05

Resource Constrained Power Constrained Thermal Constrained

Abadir and Breuer ‘85 Zhao and Upadhyaya ‘05

Chou, Saluja and Agrawal ‘94

He, Peng and Eles ‘07

 Literature Review: Resource constrained Test scheduling

Goal: Minimize total test time under resource constraints

Test compatibility graph (TCG)
BIST

Core 1 Core 2 BIST Core 3 t2

t1
X t3

t4 t6
Core 4 BIST Core 5 Core 6
X
BIST t5
 Literature Review: Resource constrained Test scheduling

Goal: Minimize total test time under resource constraints

Clique cover heuristic

 A clique is a maximal complete t2
subgraph of a graph.
 Goal: cover all nodes by minimum t1 t3
number of cliques.
 Solution:
t4 t6
(1,3,5)
(2,6)
(4) t5
 Literature Review: Resource constrained Test scheduling

Test Session
 A subset of the test set such that all the tests in the test session are
compatible.

 Next test session can start only after previous test session is completed.

Test time Test time Test time

t1 t1 t1

t3 t2 t3 t2 t3 t2

t5 t6 t4 t5 t6 t4 t5 t6 t4
Session 1 Session 2 Session 3 Session 1 Session 2 Session 3

Test scheduling Test scheduling Better solution

with equal length tests with unequal length tests For unequal length tests
 Literature Review: Power constrained Test scheduling

Goal: Minimize total test time under resource and power constraints
Solutions: t2 2
 Chou et al. (TCAD’97)
2
Graph-based heuristic t1 t3 1
 Iyengar et al. (TCAD’02) X
Mixed Integer Linear Programming
Power limit
4 t4 t6 2
 Zhao et al. (TCAD’05)
Rectangle packing heuristic
Pmax = 5
t5 3

Source: Zhao et al. TCAD’05

 Literature Review: Thermal constrained Test scheduling

:
Goal Minimize total test time under resource, power and thermal constraints
Solutions:
 Rosinger et al. (DATE’05, TCAD’06)
 Liu et al. (DFT’05)
Generate solutions of power constrained test scheduling first, then modified by
thermal constraint

 He et al. (DFT’06, ITC’07, ATS’08)

Test set partitioning and interleaving
Constraint logic programming

 Bild et al. (ICCAD’08)

Simplified thermal model
MILP formulation
Seed-based clustering heuristic
 Test scheduling: Our solution

Thermal-aware test scheduling (ITC’09)

 Superposition principle to compute thermal profile
 Scheduling algorithm
 Experimental results

Partition-based thermal-aware test scheduling (ATS’09)

 Power model
 Test partition
 Experimental results