What is a 3D IC?

Could be Heterogeneous… “Stacked” 2D (Conventional) ICs

Motivation
Interconnect structures increasingly consume more of the power and
delay budgets in modern design

Plausible solution: increase the number of “nearest neighbors” seen by

each transistor by using 3D IC design

Smaller wire cross-sections, smaller wire pitch and longer lines to

traverse larger chips increase RC delay.RC delay is increasingly becoming
the dominant factor

At 250 nm Cu was introduced alleviate the adverse effect of increasing

interconnect delay.

130 nm technology node, substantial interconnect delays will result .

 3D ICs with Multiple Active Si Layers
Motivation
• Performance of ICs is limited due to R, L, C of interconnects
• Interconnect length and therefore R, L, C can be minimized by stacking active Si layers
• Number of horizontal interconnects can be minimized by using vertical interconnects
• Disparate technology integration possible, e.g., memory & logic, optical I/O, etc.
Repeaters
Gate optical I/O devices
n+/p+ n+/p+
VILIC
Interconnect M4
delay Gate delay
1 active M3

2 Si layer M2
Delay

3 M1

Gate
Memory
T2
Analog
n+/p+ n+/p+

M’2

0.1 0.5 1 M’1

Generation (µm) Gate Via

n+/p+ n+/p+ T1

Logic
 3D Fabrication Technologies
• Many options available for realization of 3D circuits
• Choice of Fabrication depends on requirements of Circuit
System
Beam Processed Wafer Silicon Epitaxial Solid Phase
Recrystallization Bonding Growth Crystallization

Deposit polysillicon Bond two fully Epitaxially grow a Low Temp

and fabricate TFTs
-not practial for 3D circuits
due to high temp of melting
polysillicon
-Suffers from Low carrier
mobility
-However high perfomance
TFT’s
have been fabricated using
low temp processing which
can be used to implement 3D
circuits
processed wafers single cystal Si alternative to SE.
together.
-Similar Electrical Properties -High temperatures cause -Offers Flexibilty of creating
on all devices siginificant cause significant multiple layers
-Independent of temp. since degradation in quality of -Compatible with current
all chips are fabricated then devices on lower layers processing environments
bonded
-Process not yet -Useful for Stacked SRAM
-Good for applications where manufacturable and EEPROM cells
chips do independent
processing
-However Lack of
Precision(alignemnt) restricts
interchip communication to
global metal lines.
Performance Characteristics
 Timing
 Energy

With shorter interconnects in 3D ICs, both switching energy

and cycle time are expected to be reduced
 Timing
• In current technologies, timing is
interconnect driven.

• Reducing interconnect length in

designs can dramatically reduce RC
delays and increase chip
performance.

• The graph below shows the results of

a reduction in wire length due to 3D
routing.
Energy performance
Wire length reduction has an impact on the cycle time
and the energy dissipation.

Energy dissipation decreases with the number of layers

used in the design.
Energy performance graphs
 Chip Size

Device Size Limited Wire Pitch Limited

PMOS 



NMOS 

• Memory: SRAM, DRAM • Logic, e.g., µ-Processors

 Rent’s Rule

N gates

T = k NP
T = # of I/O terminals
N = # of gates
k = avg. I/O’s per gate
P = Rent’s exponent
CHALLENGES FOR 3-D INTEGRATION:
 THERMAL ISSUES IN 3-D ICs.

 RELIABLITY ISSUES IN 3-D ICs.

PRESENT SCENARIO OF THE 3-D IC
INDUSTRY
Many companies are working on the 3-D chips ,including groups at Massachusetts
institute of technology (MIT),international business machines(IBM).

First products will be memory chips called 3-Dmemory, for consumer electronics like
digital cameras and audio players. current flash memory cards for such devices are
rewritable but expensive .

The cost is so largely because the stacked chips contain the same amount of circuitry as
flash cards but use a much smaller area of the extremely expensive silicon wafers that
form the basis for all silicon chips.
ADVANTAGES OF 3-D MEMORY
Disks are inexpensive, but they requires drives that are expensive bulky ,fragile and
consume a lot of battery power.

Flash and other non volatile memories are much more rugged, battery efficient compact
and require no bulky drive technologies.

The ideal solution is a 3-D memory that leverages all the benefits of non volatile media,
costs as little as a disk, and is as convenient as 35 mm film and audio tape.
APPLICATIONS
Portable electronic digital cameras, digital audio players, PDAs, smart cellular phones,
and handheld gaming devices are among the fastest growing technology market for both
business and consumers.

Manufacturers of memory driven devices can now reach price points previously
inaccessible and develop richer, easier to use products.

Existing mask ROM and NAND flash non volatile technology force designers and product
planners to make the difficult choice between low cost or field programmability and
Flexibility.
FUTURE OF THE 3-D IC INDUSTRY
Thomson electronics, the European electronic giant, will begin to incorporate 3-D
memory chips from matrix semiconductor in portable storage cards, a strong
endorsement for the chip start up.

Matrix is working with partners including Microsoft Corp, Thomas Multimedia, Eastman
Kodak and Sony Corp. three product categories are planned: bland memory cards: cards
sold preloaded with content, such as software or music ; and standard memory
packages, for using embedded applications such as PDAs and set-top boxes .

The first Technicolor cards will offer 64 MB of memory; version with 128 MB and 192 MB
will appear later. The first 3-D chips will contain 64 MB. Taiwan Semiconductor
Manufacturing Co. is producing the chips on behalf of matrix.
CONCLUSION
The 3 D memory will just be the first of a new generation of dense, inexpensive chips that
promise to make digital recording media both cheap and convenient enough to replace
the photographic film and audio tape.

The multilayer chip building technology opens up a whole new world of design like a city
skyline transformed by skyscrapers, the world of chips may never look at the same again.
THANK YOU