Sunteți pe pagina 1din 46

Introduction to Embedded

systems

1
Contents
• Overview of Embedded systems

• Design Challenges

• Three key embedded system technologies.

2
Overview of Embedded
systems
 An embedded system is nearly any

computing system other than a desktop,
laptop, or mainframe computer.

 Some of the common examples of


Embedded Systems are given below.

3
 Consumer electronics

4
 Home Appliances

5
 Business equipment

6
 Automobiles

7
A “short list” of embedded systems
Modem s
MPEG decoders
 Anti-lock brakes
Net work cards
 Auto-focus cameras
 Automatic teller machines Net work swit ches/rout ers
 Automatic toll systems On-board navigat ion
 Automatic transmission Pagers
 Avionic systems Phot ocopiers
 Battery chargers Point -of-sale syst em s
 Camcorders Port able video gam es
 Cell phones Print ers
 Cell-phone base stations
Sat ellit e phones
 Cordless phones
Scanners
 Cruise control
Sm art ovens/dishwashers
 Curbside check-in systems
Speech recognizers
 Digital cameras
 Disk drives St ereo syst em s
 Electronic card readers Teleconferencing syst em s
 Electronic instruments Televisions
 Electronic toys/games Tem perat ure cont rollers
 Factory control Theft t racking syst em s
 Fax machines TV set -t op boxes
 Fingerprint identifiers
VCR’s, DVD players
 Home security systems
Video gam e consoles
 Life-support systems
Video phones
 Medical testing systems
Washers and dryers

8

Embedded systems have several common

characteristics.

1. Single-functioned.

2. Tightly constrained.

3. Reactive and Real time.

9
An embedded system example -- a
digital camera

digital camera system shown in Figure 2.2

10
Design challenge – optimizing
design metrics
 Obvious design goal:
◦ Construct an implementation with desired
functionality
 Key design challenge:
◦ Simultaneously optimize numerous design metrics
 Design metric
◦ A measurable feature of a system’s
implementation
◦ Optimizing design metrics is a key challenge
• 11
Design Challenges

Common relevant metrics include
1.NRE cost
2.Unit cost
3.Size
4.Performance
5.Power
6.

12

6. Flexibility


7. Time-to-market


8. Time-to-prototype


9. Correctness


10. Safety


11.Maintainability

13
Time-to-market: a demanding
design metric

 Market window

 Missing window


• Fig 2.3 Market window

14
Simplified revenue model




 Area = 1/2 * base * height
On-time = 1/2 * 2W *
 W
• Delayed = 1/2 * (W-

Fig 2.4 simplified revenue model D+W)*(W-D

Percentage total revenue loss = (W2- 1/2 *


(2W-D)*(W-D))/W2
• =(2W2-(2W2-3WD+D2))/2W2
• =D(3W-D)/2W2

15
Losses due to delayed market
entry








Fig 2.5 Losses due to delayed market entry

16
NRE and unit cost metrics

• Compare technologies by costs -- best
depends on quantity

– Technology A: NRE=$2,000, unit=$100

– Technology B: NRE=$30,000, unit=$30

– Technology C: NRE=$100,000, unit=$2

17
 total cost = NRE cost + unit cost * # of units.



Fig2.6 total cost

18
 per-product cost = (NRE cost / # of units) +
unit cost.
 Larger the volume, lower the per-

product cost.


Fig 2.7 per-product cost

19
Performance design metric
1.Latency (response time)
2.Throughput


3. Speedup

Speedup of B over A = performance of B /
performance of A

20
Three key embedded system
technologies
 Technology
– A manner of accomplishing a task, especially

using technical processes, methods, or


knowledge.
 Three key technologies for embedded systems
– Processor technology

– IC technology

– Design technology

21
Processor technology
 The architecture of the computation engine used
to implement a system’s desired functionality.

• Types of processors

– General-purpose processors -- “software”
(programmable).

– Single-purpose processors -- “hardware”.

– Application-specific instruction processors (ASIP)

22
General-purpose processors
 Programmable device used in a variety of
applications. Also known as “microprocessor”.
 Features

– Program memory

– General data path with large register file and general
ALU

E.g. Pentium


Fig 2.8 General purpose processors
23
General-purpose processors

• User benefits
 Low time-to-market
 Low NRE costs
 High flexibility
 Low unit cost (small quantity)
 High performance for some app.

• Control and computation (possibly)

• Possible drawback
 May be too big
 High unit cost (large quantity)
 Low performance for some app.

• Image and sound processing (possibly)
24
Single-purpose processors
 Digital circuit designed to execute exactly one
program.
 Features
- Contains only the components needed to execute a
single program.
- No program memory.
-
-


Fig 2.9 Single purpose processors

25
Single-purpose processors

• Benefits
 Low power
 Small size
 Low cost for large quantities
• Compare to GP

 High performing for some app.


Drawbacks

 Long time-to-market
 High NRE costs
 Low flexibility
 High unit cost (small quantity)
• Compare to GP

 Low performance for some app


26
Application-specific processors
 Programmable processor optimized for a

particular class of applications.
 Features

– Program memory.

– Optimized data path.

– Special functional units.


Fig 2.10 Application specific processors

27
IC technology
 The manner in which a digital(gate-level)
implementation is mapped onto an IC.
 Three types of IC technologies

– Full-custom/VLSI.

– Semi-custom ASIC (gate array and standard cell).

– PLD (Programmable Logic Device).


Fig 2.11 several layers of IC

 28
Full-custom/VLSI

All layers are optimized for an embedded
system’s particular digital implementation

– Placing transistors

– Sizing transistors

– Routing wires
 Benefits

◦ Excellent performance, small size, low power


 Drawbacks
◦ High NRE cost (e.g., $300k), long time-to-market
• 29
Semi-custom ASIC

Lower layers are fully or partially built

– Designers are left with routing of wires and
maybe placing some blocks.
 Benefits
◦ Good performance, good size, less NRE cost than
a full-custom implementation (perhaps $10k to
$100k)
 Drawbacks
◦ Still require weeks to months to develop

30
PLD

Programmable Logic Device

– Programmable Logic Array, Programmable Array Logic, Field
Programmable Gate Array.

• All layers already exist.

– Designers can purchase an IC.

– To implement desired functionality.
 Benefits
◦ Low NRE costs, almost instant IC availability
 Drawbacks
◦ Bigger, expensive (perhaps $30 per unit), power hungry,
slower
31

Moore’s law
 The most important trend in embedded systems
◦ Predicted in 1965 by Intel co-founder Gordon
Moore

IC transistor capacity has doubled roughly
every 18 months for the past several decades

10,00
0
1,000

Logic transistors 100


per chip 10
(in millions) 1
0.1
0.01
0.001
1981

1985

1989

1995

2001

2007

2009
1983

1987

1991

1993

1997

1999

2003

2005

32
Graphical illustration of Moore’s law



1981 1984 1987 1990 1993 1996 1999 2002

10,000 150,000,000
transistors transistors

Leading edge Leading edge
chip in 1981 chip in 2002

 Something that doubles frequently grows more


quickly than most people realize!
◦ A 2002 chip can hold about 15,000 1981 chips
inside itself

33
Design Technology
 The manner in which we convert our concept
of desired system functionality into an
implementation
 • Moore’s law
 – Exponentially increasing number of
available functions
 • Designer must keep up with Moore’s law
 – Improvement in design technology.
34
Ideal top-down design process
andproductivity enhances

35
Design Technology
Compilation/ Libraries/ Test/
Synthesis IP Verification

Syst em Syst em Hw/Sw/ Model sim ulat ./


Compilation/Synthesis: Automates specificat ion synt hesis OS checkers
exploration and insertion of
implementation details for lower
level.

Behavioral Behavior Cores Hw-Sw


specificat ion synt hesis cosim ulat ors
Libraries/IP: Incorporates pre-
designed implementation from
lower abstraction level into higher
level.
RT RT RT HDL sim ulat ors
specificat ion synt hesis com ponent s

Test/Verification: Ensures correct


functionality at each level, thus
reducing costly iterations between Logic Logic Gat es/ Gat e
levels. specificat ion synt hesis Cells sim ulat ors

To final implementation

36
Design productivity exponential
increase

10,000

(K) Trans./Staff – Mo.


1,000

100

Productivity
10


1

 0.1

 0.01
1993

2005
2001

2003
1987
1983

1991
1985

1989

1999
1997

2007
1995
1981

2009

 Exponential increase over the past few


decades

 37
The co-design ladder
 In the past:
◦ Hardware and software design technologies were
very different
◦ Recent maturation of synthesis enables a unified
view of hardware and software
 Hardware/software “co design”
 The choice of hardware versus software for a
particular function is simply a tradeoff among
various design metrics, like performance,
power, size, NRE cost, and especially
flexibility; there is no fundamental difference
between what hardware or software can
implement.
38

The co-design ladder
Sequential program code (e.g., C, VHDL)

Behavioral synthesis
Compilers (1990's)
(1960's,1970's)

Register transfers
Assembly instructions RT synthesis
(1980's, 1990's)
Assemblers, linkers
(1950's, 1960's) Logic equations / FSM's

Logic synthesis
(1970's, 1980's)
Machine instructions
Logic gates

Implementation
Microprocessor plus program bits: “software” VLSI, ASIC, or PLD implementation: “hardware”

39
Independence of processor
and IC technologies
 Basic tradeoff
◦ General vs. custom
◦ With respect to processor technology or IC technology
◦ The two technologies are independent.
◦ General-
ASIP
Single-
purpose purpose
General, processor processor Customized,

providing improved: providing improved:

Flexibility

Maintainability
Power efficiency
Performance
NRE cost Size
◦ to-prototype
Time- Cost (high volume)
Time-to-market
Cost (low volume)

◦ PLD Semi-custom Full-custom

40
The Productivity Gap
 Even with advances in design technology
 – Human still fall behind chips!!!
 • More and more designers needed…
10,00 100,000
0
1,000 10,000

Logic transistors 100 1000


per chip 10 Gap 100 Productivity
(in millions) IC capacity (K) Trans./Staff-Mo.
1 10
0.1 1
productivity
0.01 0.1

0.001 0.01
1981

1983

1985

1991

1997

2001

2003

2005

2007

2009
1987

1989

1993

1995

1999

41
Design productivity gap
 While designer productivity has grown at an
impressive rate over the past decades, the
rate of improvement has not kept pace
with chip capacity
 10,00 100,000
0
1,000 10,000

Logic transistors 100 1000


per chip 10 Gap 100 Productivity
(in millions) IC capacity (K) Trans./Staff-Mo.
1 10

0.1 1
productivity
0.01 0.1

0.001 0.01
1981

1983

1987

1989

1993

1995

1999

2003

2009
1985

1991

1997

2001

2005

2007

42
Design productivity gap
 1981 leading edge chip required 100 designer
months
 – 10,000 transistors / 100 transistors/month
 • 2002 leading edge chip requires 30,000
designer months
 – 150,000,000 / 5000 transistors/month
 • Designer cost increase from $1M to $300M

43
The mythical man-month
 The situation is even worse than the productivity gap
indicates
 In theory, adding designers to team reduces project
completion time
 In reality, productivity per designer decreases due to
complexities of team management and communication.
 In the software community, known as “the mythical man-
month” (Brooks 1975)
 At some point, can actually lengthen project completion
time!

44
The mythical man-month
• 1M transistors, 1 designer=5000 trans/month

• Each additional designer reduces for 100


trans/month

• So 2 designers produce 4900 trans/month each



Team
60000 15
16 16
50000 19 18
40000 24 23
30000
Months until completion
20000 43
10000 Individual

0 10 20 30 40
Number of designers 45
 • 1 M. Transistors; 1 designer = 5000 trans/mo;
Add. Designer = -100 trans/mo

46