c250 Slide

Lithography and Design in
Partnership: A New Roadmap

Andrew B. Kahng
UCSD Depts. of CSE and ECE
abk@ucsd.edu
http://vlsicad.ucsd.edu/
Outline
• Two Cultures, Two Roadmaps

• Lithography changes the Design roadmap
• Design changes the Lithography roadmap
• Toward a shared Litho-Design roadmap
SPIE Advanced Lithography 2008 Andrew B. Kahng 2

Two Mindsets
PROCESS DESIGN
• Golden model of Chip • Golden model of Process
• Polygon data • SPICE
• Don’t know how it was obtained • Don’t know how it was obtained
• To sell the wafer, meet spec • To sell the chip, meet spec
• power and timing
• shapes and currents
• Mechanism for checking:
• Mechanism for checking:
• verify at “corners”
• measure silicon • Don’t know how they were
obtained

Two Kinds of “Beyond the Die”
PROCESS DESIGN
Package
Wafer
Die
Board
Wafer-to-Wafer Lot-to-Lot System

Two Roadmaps
CD Uniformity
MEEF dense line Chip size
MEEF isolated Leakage power
line Dynamic power
Linearity Max frequency
CD MTT MTTF
Data volume Reuse
Defect size Circuit families

What Is The Connection?
LITHO DESIGN
CD uniformity Chip size
MEEF dense Leakage power
MEEF isolated Dynamic power
Linearity Max frequency
CD MTT MTTF
Data volume Reuse
BSIM Model
Defect size Circuit families
WL
• Device A1
VDD
A2
nr
•
nl C2
Model C1
B1 B2
• Circuit BLb BL
• Product
• Cost
Outline


1. Layout Restriction: RDRs
• RETs, DRCs, physics  Risk, Margin, Cost
• Give designers freedom from choice
• Area cost of RDRs = one-time, inevitable ‘reset’
Irregular active geometry

Beyond L3GO: All geometry
Irregular poly geometry
represented as lines and dots
Off-grid contact placement
Requirement: Grid-Based Layout
• Not a slam dunk
– Logic: contact landing, diffusion, area optimization
– SRAM: SNM  multiple diffusion widths
– Clouded by imperfect cost and feasibility analyses
• Win: scaling, model guardband reduction
reduction,
TAT
45nm 45nm (IBM, IEDM06)

Design Impact of Model Guardband
• Random Defect Yield (Yr) • Parametric Yield (Ys)
– Strong function of area (A) – Function of design guardband
• Guardband reduction  less • Guardband reduction  less
design time, less chip area ! yield at wafer sort
– (Timing closure is easier) • Example: normal distribution
with BC / WC = -3σ / +3σ
Pr ( # defects on chip = k )
4. 0
Γ(α + k ) ( Ad α) k
= ⋅
3. 0
k!Γ(α) (1 + Ad α)α+k 34.1%
0. 0 1. 0 2. 0
34.1%
0.1% 13.6% 13.6% 2.1%
k = 0  Binomial PDF -3σ -2σ -1σ 1σ 2σ 3σ
−α – x% guardband reduction
Yr = (1 + Ad α ) 1   3(1 − 0.01x)   − 3(1 − 0.01x) 
Ys ( x%) = erf   − erf  
2  2   2 
Worst case (α = ∞ ): Poisson
− Ad – 0% reduction: Ys=0.9973
Y =e
r – 40% reduction: Ys=0.9281
Guardband Impact = Methodology Lever
• UCSD 2007: Design methodology can use model guardband as lever to
trade off TAT, chip area and power, and sort yield
• Complements variability reductions in the manufacturing process
– Random defect yield will increase
– Parametric yield will decrease
– TAT will decrease
– (Moore’s Law: 1% per week)
# of good dice per wafer
158
156
154
152
no clustering
150
alpha=0.42
148 alpha=0.43
alpha=0.44
146
alpha=0.45
144 alpha=0.5
142
alpha=1
alpha=10
140 alpha=1000
138
0 10 20 30 40 50 60
Reduced GB (%)
• Example: 20% guardband reduction  4% increase in good die /wafer

2. Double Patterning Lithography (DPL)
Desired Combined
First Mask Second Mask
pattern exposure
• ORAMEX (Ordinary Resist And Multiple Exposure), IBM 1998

• Challenges
– Equipment: overlay margin
– Design: layout decomposition, design rules, new OPC for DPL
Layout Splitting and Coloring
Layout Fracturing
Conflict Graph Construction Node Splitting

for Touching Features
Conflict Cycle Detection

ILP based or heuristic
Graph Coloring
Conflict No
Cycle?
• Find min-cost color assignment
– Non-touching features with
Yes
0 < d(i,j) < t  different colors
Node Splitting for – Touching features assigned different
Conflict Cycle Removal colors  incur cost cij

Smart Dividing Point Selection
= +
= +
• Split polygons to have maximum overlap

• Reduce CD variation from LES, misalignment
Limits of Layout Decomposition
o1
o2
= +
Layout Decomposition Two Masks with Extended Overlap Design Change

(Increase space)
Decomposition (1) Decomposition (2) Design Change Design Change

(Increase space) (Reduce size)
• Require DPL-compliant design

Hierarchical ILP Solver (UCSD 2008)
t # conflict overlap lengths Runtime
• Testcase: 0.5mm
cycles x 0.5mm block, TSMC 90nm
(s)
49nm 70nm 72nm
– 20K standard cells
– High layout
60 0
density:
0
90%0utilization
0 101.4
• GDS
64 scaled
123 down
0 by 0.40 0 109.9
68  minimum
251 width:
0 40nm
125 0 104.9
72  minimum
728 space:
0 56nm
125 295 99.4
• Vary
76 distance
737 threshold
0 t from295
125 60nm to94.1
88nm
80
– 1.1 770 times minimum
to 1.6 0 125
spacing295 93.6
84 778 0 125 295 92.6
• 88Layout decomposition
872 97 125 295 93.0
– Solves all conflict cycles with largest possible overlap lengths
• Scalable runtime from hierarchical graph decomposition
– 32nm dense layout: ~2400 sec / mm2, 1 CPU, fully parallelizable

3. Analyses of Bimodal CD Distribution
• Bimodal distribution in DPL
– Poly gates made by two independent processes
– Gate CD distributions in two groups can differ
• Loss of correlations (spatial, line-space)
Mean of Mean of
Group 1 Group 2
Group 1 Group 2 Source: Wikipedia

Unimodal Modeling Is Pessimistic
• Conventional unimodal representation does
not capture bimodal process variation
G1G2
BC of G1 WC of G2
BC of G2 WC of G1
• DPL modeling, analysis requirements = ?

Monte Carlo Simulation
• SPICE model Unimodal
– 65nm, Typical corner (TT), 1.0V,
25°C Bimodal
• SPICE circuit Group2
– 65nm NVT: Nominal CD is 2n
“60nm”
54 56 59 61 64 66
• CD variation model 60
– Assumption: small mean Best CD Worst CD

difference MeanG1 = 59nm, 3σ G1 = 5nm
• Group1: N(meanG1=59nm, 3σ=5) MeanG2 = 61nm, 3σ G2 = 5nm
• Group2: N(meanG2=61nm, 3σ=5)
Meanuni = 60nm, 3σuni = 6nm
• Comparison
– {Rise/Fall Delay, Leakage} of
unimodal and bimodal distribution

Path Delay, Leakage (10K MC Iterations)
• Bimodal distribution  two distinct simulation cases
– DPL1: gate (2i+1) is in Group1 and gate (2i) is in Group2
– DPL2: gate (2i+1) is in Group2 and gate (2i) is in Group1
Delay (mean) Leakage (mean)
fall rise Input 0 Input 1
5.00E-11 5.00E-08
4.95E-11
4.00E-08
4.90E-11
3.00E-08
4.85E-11
4.80E-11
2.00E-08
4.75E-11
1.00E-08
4.70E-11
4.65E-11 0.00E+00
DPL1 DPL2 DPL1 DPL2 DPL1 DPL2 DPL1 DPL2
Bimodal Unimodal Bimodal Unimodal Bimodal Unimodal Bimodal Unimodal
Delay (sigma) Leakage (sigma)

2.5E-12 fall rise 2.00E-06 Input 0 Input 1
2E-12
1.50E-06
1.5E-12
1.00E-06
1E-12
5.00E-07
5E-13
0 0.00E+00
DPL1 DPL2 DPL1 DPL2 DPL1 DPL2 DPL1 DPL2
Bimodal Unimodal Bimodal Unimodal Bimodal Unimodal Bimodal Unimodal
• Unimodal representation is too pessimistic

• Different characteristics of DPL1 and DPL2  coloring affects timing
Severe Methodology Implications
• Pervasive design flow changes

– SPICE modeling to capture bimodal distribution ?
– Cell characterization: multiple timing libraries for DPL1,
DPL2 ?
– Timing modeling based on actual placement and DPL mask
coloring of each cell ?
– New spatial correlation modeling (intra-exposure, transistor-
level) ?
• Note:
– Path delay variation may actually decrease, but this cannot
be exploited due to loss of spatial correlations

Outline


1. Power-Limited Frequency Roadmap
• Power, thermal limits to maximum clock frequency (UCSD 2007)
– ITRS MPU (HP) frequency roadmap updated in 2007
120
Frequency (GHz)
100 ITRS 2005 ITRS 2007

80 ~1.6× per node
(based on device enhancement)
60
40 1.25× per node

20 (to meet power requirement)
0
2013
2019
2011
2015
2017
2021
2009
2007
Year
• Ripple effect  relaxed lithography CD 3σ requirement ?
Intrinsic Physical
Frequency CD Control
Delay (CV/I) Lgate
Requirement Requirement
Requirement Requirement

2. Design Awareness: Slack
• Positive timing slack can be exploited to reduce power and relax RET, litho requirements
3 -1
Tarrival
1+2 5 -3
Trequired
2
+2
7-7
1-1
10 20
2 -2
1
0
Gates
1
of positive-slack
0
-5
0
2 cells 5can have larger
4 - 4
1+1 CD variation budget!
2-1
Slack = Trequired – Tarrival

CLK CLK

Design Awareness: Redundancy
• Redundant features require less pattern fidelity
• Implications
– RET complexity, inspection + defect disposition flows
– Reduced impact of process variability on design
Redundant Via Non-Tree Routing Metal Dummy Fill

(Loop)

3. “Design For Equipment”
• Systematic variation impacts  Mitigate or Exploit
– OPC + fracturing: Major field, subfield boundary aware?
– Overlay error: x- vs. y-direction bias of correction depending on circuit and layout?
– Other: Model-based OPC error, CMP pattern-dependence
• Example: ASML DoseMapper

– APC: global CD uniformity in step-and-scan tool
• Idea
– Increase dose for timing-critical device  more speed
– Decrease dose for non-critical device  less leakage
• Two directions for optimization
– Given cell placement, optimize the dose map
– Given dose map, optimize the placement

ASML DoseMapper
• DoseMapper
– Adjust exposure dose to improve CDU
– Compensate ACLV and AWLV
• Unicom (slit direction)
– Change intensity profile across slit
– Actuator: variable-profile gray filter
– Maximum correction range: +/- 5%
• Dosicom (scan direction)
– Change intensity profile along scan direction Adjust exposure dose
– Dose profile can have higher-order corrections
– Maximum correction range: +/- 5%
Direction
Scan
• Dose Sensitivity
– Linewidth has approximately linear relationship
Slit profile
with exposure dose
– E.g., dose sensitivity (DS): -2nm / % Slit and Scan directions

Placement-Aware Dose Map
Traditional: same CDs UCSD (2007): different CDs
• Same target CD for all devices • Setup-timing critical device

• Leaves parametric yield  larger dose  faster switching
improvement on the table • Hold-timing critical device
• No “design awareness’’  smaller dose  less leakage
• Improve timing yield without
leakage penalty

Dose Map-Aware Placement
Dose (D1) D1
path P1 path P1
path P2 path P2
Dose (D2) D2
Before Cell-Swapping After Cell-Swapping

Dose: D1<D2, Timing Criticality: P1>P2
• Given a dose map and a placement, swap critical cells to high-dose

regions and non-critical cells to low-dose regions
• Heuristic priorities based on (1) number of critical paths passing through
cell, and (2) slacks of critical paths

Example DoseMap Result (UCSD 2007)
10 x 10 20 x 20 20 x 50
Nom Lgate
DMopt imp. (%) DMopt imp. (%) DMopt imp. (%)
MCT (ns) 1.990 1.844 7.331 1.810 9.048 1.805 9.327
Pleakage
2430.2 2626.2 -8.066 2527.9 4.020 2433.6 0.138
(µW)
Runtime
-- 35.5 47.6 142.0
(s)
Dose optimization results with different grids

Test case: TSMC90, ~20K standard cells
•
DoseMap Optimization: 9.3% cycle time improvement (0.13% leakage increase)
• Essentially: near-maximum frequency gain, zero leakage penalty
–
DoseMap Optimization + dosePlace: 9.6% cycle time (0.2% leakage)
•
Need roadmap of enablement

Outline


Why A Shared Roadmap?
• Process: changes what is possible
• Design: realizes what is possible
• Neither by itself guarantees market success of ICs
– More Than Moore:
Embedded software
– ITRS Consumer Stationary Driver
Architecture
1000
– Stacked integration
48% CAGR
– … Performance
– “Dark100
Future” (2000 Japan DA Show keynote): electronics
30% CAGR
industry finds workarounds for both process# and design
performance
Normalized
cores
If we do not hang together, we

10 14-17%will
CAGR
Device speed
surely hang separately
1
2014
2016
2020
2018
2012
2008
2006
2010
• If either is too risky --

orBenjamin
expensiveFranklin
 neither wins
Goal: Principled Connections
Litho and RET metrics
Electrical and Design metrics
Layout practices and design rules
• Balanced technology requirements

• Balanced R&D investments
“Shared Red Bricks”
• Example: Line End Taper

Which Shape Is Best For Design?
Moderate Aggressive
Poly
(b) Slope
Best
DOF
(c) Bulge
(a) Typical Worst

DOF
(d) Asymmetry
Active

Line-End Tapering
• Tapering
– A gradual lessening of width towards one end
– We use the word “taper(ing)” to describe the shape
of a polysilicon line-end
• Traditional Taper Metric
Make as rectangular as possible, meeting line-end
gap (LEG) and line-width (LW0) rules
Line-End Shortening
LW0
LEG Line-End Bridging

Superellipse-Based Shape Model
• “Academic” basis for shape modeling (UCSD 2007)
• Superellipse y
b
n n
x y −k a
x
+ =1
a b −c Diffusion
Gate
• Parameters of superellipse y
c
– LEE: b’= b-c+k b’
θ
– a: gate length = size of 2*a o a x o
k
– n: ‘roundness’ of superellipse
– k: shift in y-direction (Bulge)
– θ : rotation (Asymmetry)
(a) Bulge (b) Asymmetry
Electrical Impact of Line-End Extension
Increasing LEE
• Line-end extension increases Cg
Increasing Field
– fringe capacitance between line-end
extension and channel
• Cg affect Vth , following Vth model

equation. Vth
– Cg increase  Vth decrease
– Cg decrease  Vth increase V fb + 2ψ B
Cg
• Ion and Ioff are functions of Vth
– Vth increase Ion, Ioff decrease
– Vth decrease  Ion, Ioff increase misalignment
• Misalignment error can make

large difference in Ion and Ioff

Capacitance Modeling of LEE
• LEE makes fringing fields to the channel
– Fringing field weakens as distance increases
Oxide
Gate on channel Gate on LEE
ti
Ctaper,i
hi
Poly
li
Cedge
Active tox Active
Poly
3D view Side view
β
 ti 
C gate = Cchannel + Ctaper
α
Ctaper ,i = li ⋅ 
h 

 i 
1/ n
 h −k
n

N li = 2a1 − i 
 b −c 
C taper = C edge + ∑ C taper ,i ,  
l
i =1 Cedge = λ ⋅ 0
Lnom
Location-Based Current Model
• LEE affects current (Ion and Ioff) at gate edge
– As LEE area increases, current at gate edge increases
sharply. Increase depends on Ctaper
* From DaVinci i
i = i + ∆i Ctaper _ top ) i+ ∆i (Ctaper _ bottom )
i i i( 0
∆i (Ctaper _ top )
2.70E+07
0
∆i (Ctaper _ bottom )
0
channel
2.60E+07
i0
2.50E+07
+ 60nm
0
40nm
channel
10nm + 0
channel
Incremental current
0 Incremental current
∆ion ∝ ( Ctaper )
Current without LEE effect
due to top LEE − distance α due to bottom LEE
2.40E+07
s=1 s=3 … channel

⋅ e … s=N
2.30E+07
s=2 s=N-1
I model = ∑s =1 i ( s ) ≅ I measure
2.20E+07
N
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55
80nm fixed 80nm fixed

Diffusion
Varied:
Gate 70nm fixed
10, 40, 60nm
Diffusion
Electrical Difference ≠ Geometric Difference
y Drawn Gate
• Must consider electrical b Large ‘n’
impact of shape o a x
Diffusion Small ‘n’
• Lithographers prefer Gate
rectangular shapes with xn y −k n

+ =1
a b −c
sharp edges
• This comes at cost of 1.48E-10
Ioff vs. LEE shape
5.00
litho + RET complexity 1.47E-10

Ioff(A)
4.50
4.00
Ioff Reduction(%)
1.46E-10 Ioff Reduction (%) 3.50
• Is there a sweet spot? 1.45E-10 3.00
Ioff (A) 1.44E-10 2.50
1.43E-10 2.00
1.50
1.42E-10
1.00
1.41E-10 0.50
1.40E-10 0.00
2.5 3.0 3.5 4.0 4.5 5.0

Superellipse Exponent (n)

Example: LEE Rule vs. Bitcell Leakage
• LEE shape changes LEE length vs. Ioff relationship
• Sweep LEE and ‘n’ of super-ellipse, measure Ioff
2.00E-09
14
n=2.5
Large ‘n’ 1.80E-09
n=3.0
12
1.60E-09 n=3.5
n=4.0
Small ‘n’ 10
1.40E-09 n=4.5
n=5.0
8
1.20E-09 Area Reduction (%)
6
1.00E-09 Poly Contact
8.00E-10 Diffusion NWell 4
Small ‘n’
6.00E-10 2
Large ‘n’
4.00E-10 0
100 90 80 70 60 50 40 30 20
LEE (nm)
Based on taper shape, LEE can be

optimized to reduce bitcell size
Summary
– Increasingly linked
– Inevitable RDRs: sooner than later
– DPL: new layout and analysis technology requirements
– Macro effects: frequency  Lgate  3σ
– Design awareness
– Design for Equipment
– Compelling motivation: Looming workarounds
– Let’s get to work !!!
THANK YOU!

Tearing ITRS-Lithography Roadmap
• CD tolerance is major factor of impacting
power/timing variability for 65nm and below
• Developing design methods that overcome variability
requires reasonably accurate CD tolerance estimates
• Problem in current ITRS-litho roadmap
– No breakdowns for across field, across wafer, across lot, etc
– No breakdowns for random, systematic
– No breakdowns for detailed systematic factors
• Gate CD control includes errors from all sources due to masks,
imperfect OPC, ET/DOF, and resist and all spatial length scales
(across field, across wafer, between lots)
• We need to make sure we are being realistic in terms
of what tolerances we quote, and what type of layout
they are predicted for
ACLV CD Tolerance Factors in Litho Roadmap
CDVar = αACLV 2 + βAWLV 2 + λALLV 2

ACLV = Systematic 2 + Random 2
ACLV = Across Chip Linewidth Variation
ACWV = Across Wafer Linewidth Variation
ALLV = Across Lot Linewidth Variation
ITRS Factor ITRS Factor Derating Factor
Linearity/MTT Systematic Linearity/MTT 12%
Visible Uniformity Systematic Visible Uniformity 10%
LER Random LER 10%
Overlay Random Overlay 8%
Proximity Systematic Proximity
Invisible ET/DOF Systematic Invisible ET/DOF 40%
Resist Systematic Resist
Mask Systematic Mask
• Only ACLV CD tolerance extracted using detrating factor

– Set 80% derating factor for ACLV (α=80%, β=10%, λ=10%)
• All tolerance factors are not in roadmap
– Litho-roadmap needs to show other systematic factors (proximity, ET/DOF, etc)
Extract CD Tolerance from Litho Roadmap
LGATE Tolerance Computation from 2005 ITRS
2005 2006 2007 2008 2009 2010 2011 2012 2013
Table 69a
MPU gate length (nm) 32 28 25 23 20 18 16 14 13
Table 77a
LER (3 sigma) (nm) 4.2 3.8 3.4 3 2.7 2.4 2.1 1.9 1.7
Table 78a
Gate CD control (3 sigma) (nm) 3.3 2.9 2.6 2.3 2.1 1.9 1.7 1.5 1.3
Overlay (3 sigma) (nm) 15 13 11 10 9 8 7 6 6
Mask magnification 4 4 4 4 4 4 4 4 4
MEEF - isolated lines 1.4 1.4 1.6 1.8 2 2.2 2.2 2.2 2.2
CDU - isolated (3 sigma) (nm) 3.8 3.4 2.6 2.1 1.7 1.3 1.2 1.1 1
MEEF - dense lines 2 2 2.2 2.2 2.2 2.2 2.2 2.2 2.2
CDU - dense (3 sigma) (nm) 7.1 6 4.8 4.3 3.8 3.4 3 2.7 2.4
Linearity (nm) 13 11 10 9 8 7.2 6.4 5.6 5.1
CD mean to target (nm) 6.4 5.6 5.2 4.6 4 3.6 3.2 2.8 2.6
Calculations
CDU - isolated lines (3 sigma) (nm) 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
CDU- dense (3 sigma) (nm) 0.4 0.3 0.3 0.2 0.2 0.2 0.2 0.1 0.1
Linearity + mean to target (nm) 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.3 0.2
derated overlay (3 sigma) (nm) 1.2 1.0 0.9 0.8 0.7 0.6 0.6 0.5 0.5
mask/proximity/exposure/DOF/resist 2.2 2.0 1.8 1.6 1.4 1.3 1.2 1.0 0.9
rss of the systematic numbers (nm) 2.3 2.0 1.9 1.6 1.5 1.4 1.2 1.1 0.9
plus the random variations (nm) 2.6 2.3 2. 1.8 1.7 1.5 1.4 1.2 1.0
1
% of physical gate length 8 8 8 8 8 8 9 9 8
• Systematic/random variations are divided

• Each factor is divided by the derating factor
–  help designer who tries to reduce CD tolerance of each factor
Require More Metrics in ITRS DFM Roadmap
DFM Roadmap
• Lithography (DPL)
– Difference of mean
– CD variability for each process
– Vth variability for each process
• Other metric for design
– % area of redundancy circuit
– Variability of difference
between low- and high-Vth
• DFM Tool
– Requires DFM tool metric
– Accuracy should be supported Modeling Roadmap
by ITRS-Modeling Accuracy
CD (photo/etch) prediction
– Fast simulation in circuit level Process Junction depth
is also required as well as Topography estimation
Ion/Ioff accuracy
accuracy Device Long-channel Vt
Vt rolloff
Circuit delay
Circuit I-V error
Parasitic C-V

Guardbands: Inevitable? At What Cost?
• Process change: O(weeks)
• Design change: O(days-months)
– But takes O(months) to assess in silicon
ec na mr of r e P
Technology Node
• Design tweak to fit process : impossible

• Process tweak to fit design : what we do today
• SPICE, RCX models are fixed  guardbands
inevitable
• What is the cost of guardbands to the design?

Timing and Leakage Optimization Flow
• Dose Map opt
Timing
– Input Original Design
Analysis
– Coeff calibration Dose map
– Timing analysis Dose map
Delay
– Opt.
Dose map opt Cell Library Dose Map
– Optimal dose map
Optimal
• Placement opt Dose map
– Update design
– Timing analysis Timing Updated
– Critical path Analysis design
identification Placement
– Dose-aware place Critical Placement Optimized
– Legalization path Opt. design
– ECO routing

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Lithography and Design in

Partnership: A New Roadmap

• Two Cultures, Two Roadmaps

SPIE Advanced Lithography 2008 Andrew B. Kahng 2

SPIE Advanced Lithography 2008 Andrew B. Kahng 3

Wafer-to-Wafer Lot-to-Lot System

SPIE Advanced Lithography 2008 Andrew B. Kahng 4

SPIE Advanced Lithography 2008 Andrew B. Kahng 5

• Two Cultures, Two Roadmaps

SPIE Advanced Lithography 2008 Andrew B. Kahng 7

Irregular active geometry

45nm 45nm (IBM, IEDM06)

SPIE Advanced Lithography 2008 Andrew B. Kahng 9

0.1% 13.6% 13.6% 2.1%

k = 0  Binomial PDF -3σ -2σ -1σ 1σ 2σ 3σ

• Example: 20% guardband reduction  4% increase in good die /wafer

SPIE Advanced Lithography 2008 Andrew B. Kahng 11

• ORAMEX (Ordinary Resist And Multiple Exposure), IBM 1998

Conflict Graph Construction Node Splitting

Conflict Cycle Detection

SPIE Advanced Lithography 2008 Andrew B. Kahng 13

• Split polygons to have maximum overlap

Layout Decomposition Two Masks with Extended Overlap Design Change

Decomposition (1) Decomposition (2) Design Change Design Change

• Require DPL-compliant design

SPIE Advanced Lithography 2008 Andrew B. Kahng 16

Group 1 Group 2 Source: Wikipedia

• DPL modeling, analysis requirements = ?

– Assumption: small mean Best CD Worst CD

SPIE Advanced Lithography 2008 Andrew B. Kahng 19

Delay (sigma) Leakage (sigma)

• Unimodal representation is too pessimistic

• Pervasive design flow changes

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• Two Cultures, Two Roadmaps

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100 ITRS 2005 ITRS 2007

40 1.25× per node

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Slack = Trequired – Tarrival

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Redundant Via Non-Tree Routing Metal Dummy Fill

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• Example: ASML DoseMapper

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Traditional: same CDs UCSD (2007): different CDs

• Same target CD for all devices • Setup-timing critical device

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Before Cell-Swapping After Cell-Swapping

• Given a dose map and a placement, swap critical cells to high-dose

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MCT (ns) 1.990 1.844 7.331 1.810 9.048 1.805 9.327

Dose optimization results with different grids

Need roadmap of enablement

• Two Cultures, Two Roadmaps

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If we do not hang together, we

• If either is too risky --

Electrical and Design metrics

Layout practices and design rules

• Balanced technology requirements

• Example: Line End Taper