Efficient Implementation of Digital

Filters with Use of Advanced

Synthesis Methods Targeted FPGA
Architectures

-:GUIDED BY:- -:PROJECT MEMBERS:-

SHOBHA S. GOUDAR ABHISHEK RANJAN (1SI07EC004)
ASSISTANT PROFESSOR, DEPARTMENT OF E & C ASHUTOSH KUMAR SINGH (1SI07EC019)
S.I.T(TUMKUR) GAURAV KUMAR (1SI07EC044)
GYAN RANJAN KUMAR (1SI07EC047)
WHY IMPLEMENT DIGITAL FILTERS??
 Much better signal to noise ratios

 Performs noiseless mathematical operations

 Strong option for removing noise, shaping spectrum

 Minimizing inter-symbol interference in communication

architectures

 Making the hardware requirements relatively simple

and compact
ADVANTAGES OF FPGA IMPLEMENTATION

 Higher sampling rates

 Lower costs

 Design and test cycle can be completed rapidly.

 Independence from problems like thermal noise.

 CONVENTIONAL APPROACH

 Primary digital signal processing operation

 One clock-cycle is required for each tap delay register

 Implemented as multiply-accumulate (MAC) algorithms

with use of special DSP devices
 CONVENTIONAL APPROACH
Area efficient when implemented using shared
multiply-accumulate operations.

Based on the concept of RISC processors.

Performance decreases on large order filters.

 PROPOSED APPROACH

Increase the performance of digital system.

Special techniques such as distributed arithmetic.

 PROPOSED APPROACH

 DA technique

 Efficient technique to implement on FPGAs

 Significantly increases the performance of implemented filter.

 Replaces the explicit multiplications by ROM Lookups.

 PROPOSED APPROACH
The block RAM of the FPGA’s are used to implement the Distributed
Arithmetic logic, saving precious logic gates of the device.

The computation speed can be significantly increased

Filter sample rate does not decrease with an increase in filter order

Offers highest performance in FPGAs.

 IMPLEMENTATION
Matlab for analysis

ModelSim for simulation

Xilinx ISE for implementation

Spartan 3 based FPGA platform with daughter

card for ADC/DAC.
 IMPLEMENTATION
VERIFICATION:-
The design will be verified using a Verilog test
bench or VHDL Code.

The vectors required to test the valid

conditions will be generated using Matlab.
IMPLEMENTAION
ChipScope Pro
Core Generator
Instantiate... Synthesize...
Generate.. cores into design without
.ILA,ICON Instantiating
HDL ChipScope cores
CORES… source

OR
ChipScope Pro
Core Inserter

Synthesize... Connect... Insert..

design with buses and ICON, ILA
cores in it internal signals to cores into synthesized
cores design.

Implement
design

Select..
Bit stream
view..
waveform
 REFERENCES
 Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, and
Tadeusz Luba, “Efficient Implementation of Digital Filters
with Use of Advanced Synthesis Methods Targeted FPGA
Architectures”, 8th Euromicro conference on digital system
design (DSD’05), IEEE
 XilinxApplication Note, The role of distributed arithmetic
in FPGA-based signal processing
www.xilinx.com/appnotes/theory1.pdf
 Computer Society, 2005. Stanley A. White, “Applications
of Distributed Arithmetic to Digital Signal Processing: A
Tutorial Review,” IEEE ASSP Magazine, July, 1989
THANK YOU