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Course Conducted by Shuvodip Das, Lecturer, Department of ETE, Prime University, Bangladesh.
logic circuits y We will apply the knowledge of Boolean Algebra to realize these circuits y First we will look at Combinational Logic Circuit y Unlike Sequential Logic Circuits whose outputs are dependant on both their present inputs and their previous output state giving them some form of Memory, the outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic "0" or logic "1", at any given instant in time as they have no feedback, and any changes to the signals being applied to their inputs will immediately have an effect at the output. In other words, in a Combinational Logic Circuit, the output is dependant at all times on the combination of its inputs and if one of its inputs condition changes state so does the output as combinational circuits have "no memory", "timing" or "feedback loops".
combinations to an output such that the current output depends only on the current input values. y combinational circuits have "no memory", "timing" or "feedback loops".
NOR or NOT gates that are "combined" or connected together to produce more complicated switching circuits. These logic gates are the building blocks of combinational logic circuits.
Karnaugh Map
Logic Diagram
0 1 1 0
AB
Logic Circuit
AB
table. y 2nd Step: From the truth table, we have expressed the boolean expression as X ! A B A B y 3rd Step: Given boolean expression is already in simplified form. So, no further simplification will be required. y 4th Step: From the simplified boolean expression, we have drawn the logic circuit and verified its operation.
inputs are high then output should be high. Construct the circuit. y Solution: A B C X
y y y
A B C X
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 1 0 1 1 1
A BC AB C ABC ABC
! B (C A C ) A B C ! B ( C A )( C C ) A B C ! B (C A ) A B C ! AB ! AB ! AB ! AB ! AB BC A B C C (B A B ) C ( B A )( B B ) C (B A) BC CA
Half Adder
y Adding two single-bit binary values, X,Y produces a sum S bit and a carry out C-out bit. y This operation is called half addition and the circuit to realize it is called a half adder.
X 0 0 1 1
X Y
Y 0 1 0 1
S 0 1 1 0 Half Adder
C-out 0 0 0 1
S C-OUT
Sum S
C-out
Full Adder
y
Adding two single-bit binary values, X,Y with a carry input bit Sum S C-in produces a sum bit S and a carry out C-out bit.
XY C-in
00 0
0 1
01
2 3
11
6 7
10
4 5
1
C-in
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
C-in 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1
C-out 0 0 0 1 0 1 1 1
Carry C-out
XY C-in
00 0 1
0 1
01
2 3
11
6 7
10
1 1
4 5
1
Y
C-in
XYC-in
Sum S
Y C-in
XYC-in
XYC-in
X Y
XY
C-out
Full Adder
S
C-in
X C-in Y C-in
XC-in
C-out
YC-in
Sum S
C-out
Full Adder
S
C-in
Y X C-in Y C-in
XY
XC-in
C-out
YC-in
full adders. y Each full adder represents a bit position j (from 0 to n-1). y Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1. y The output of a full adder at position j is given by: Sj = Xj Yj Cj Cj+1 = Xj .Yj + Xj . Cj + Y . Cj
y In the expression of the sum Cj must be generated by the full adder at the lower position
j-1.
y The propagation delay in each full adder to produce the carry is equal to two gate delays
= 2(
y Since the generation of the sum requires the propagation of the carry from the lowest
position to the highest position , the total propagation delay of the adder is approximately: Total Propagation delay = 2 n(
Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3
X3X2X1X0
Y3Y2Y1Y0
C4
C-out
4-bit Adder
C-in
C0 =0
S3 S2 S1 S0
Sum Output
X3
Y3
C3
X2
Y2
C2
X1
Y1
C1
X0
Y0
C4
C-out
Full Adder S3
C-in
C-out
Full Adder S2
C-in
C-out
Full Adder S1
C-in
C-out
Full Adder S0
C-in
C0 =0
Sum output
Larger Adders
y Example: 16-bit adder using 4, 4-bit adders y Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a
16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position.
Data inputs to be added X (X0 to X15) , Y (Y0-Y15)
X3X2X1X0 Y3Y2Y1Y0 X3X2X1X0 Y3Y2Y1Y0 X3X2X1X0 Y3Y2Y1Y0 X3X2X1X0 Y3Y2Y1Y0
C16
C-out
4-bit Adder
S3 S2 S1 S0
C-in
C12
C-out
4-bit Adder
S3 S2 S1 S0
C-in
C8
C-out
4-bit Adder
S3 S2 S1 S0
C-in
C4
C-out
4-bit Adder
S3 S2 S1 S0
C-in
C0 =0
Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 n( ! x 8( !(
or 32 gate delays
Carry Look-Ahead Adders Looky The disadvantage of the ripple carry adder is that the propagation delay of adder (2 nD )
increases as the size of the adder, n is increased due to the carry ripple through all the full adders.
y Carry look-ahead adders use a different method to create the needed carry bits for each full
y To eliminate carry ripple the term Ci is recursively expanded and by multiplying out, we
Carry Look-Ahead Adders Looky For a 4-bit carry look-ahead adder the expanded expressions for all carry
bits are given by: C1 = G0 + P0.C0 C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0 C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0 C4 = G3 + P3.G2 + P3.P2.G1 + P3 . P2.P1.G0 + P3.P2.P1.P0.C0 where Gi = Xi .Yi Pi = Xi + Yi
y The additional circuits needed to realize the expressions are usually referred
to as the carry look-ahead logic. y Using carry-ahead logic all carry bits are available after three gate delays regardless of the size of the adder.
4-bit CLA
The disadvantage of the carry-lookahead adder is that the carry logic is getting quite complicated for more than 4 bits. For that reason, carry-look-ahead adders are usually implemented as 4-bit modules and are used in a hierarchical structure to realize adders that have multiples of 4 bits. Figure 6 shows the block diagram for a 16-bit CLA adder. The circuit makes use of the same CLA Logic block as the one used in the 4-bit adder.
X 229 Y - 46 183
Half Subtractor
y Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces a difference bit
subtractor.
Inputs
X 0 0 1 1
Y 0 1 0 1
D 0 1 1 0
B-out 0 1 0 0
X Y
Half Subtractor
D B-OUT
B-out
Full Subtractor
y Subtracting two single-bit binary values,Y, B-in from
a single-bit value X produces a difference bit D and Difference D XY a borrow out B-out bit. This is called full subtraction.
B-in
00 0
0 1
01
2 3
11
6 7
10
4 5
1
B-in
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
B-in 0 1 0 1 0 1 0 1
D 0 1 1 0 1 0 0 1
B-out 0 1 1 1 0 0 0 1
Borrow B-out
XY B-in
00 0 1
0 1
01
2 3
11
6 7
10
4 5
1 1
Y
B-in
XYB-in
Difference D
Y B-in
XYB-in
XYB-in
X Y
XY
B-out
Full Subtractor
D
B-in
X B-in Y B-in
XB-in
B-out
YB-in
Difference D
B-out
Full Subtractor
D
B-in
Y X B-in Y B-in
XY
XB-in
B-out
YB-in
n-bit Subtractors
An n-bit subtracor used to subtract an n-bit number Y from another n-bit number X (i.e X-Y) can be built in one of two ways:
y By using n full subtractors and connecting them in series, creating a borrow
ripple subtractor:
y Each borrow out B-out from a full subtractor at position j is connected to the
y By using an n-bit adder and n inverters: y Find twos complement of Y by: y Inverting all the bits of Y using the n inverters. y Adding 1 by setting the carry in of the least significant position to 1 y The original subtraction (X -Y) now becomes an addition of X
Subtracts two 4-bit numbers: Y = Y3 Y2 Y1 Y0 from X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the difference D = D3 D2 D1 D0 , B-out = B4 from the most significant position j=3
B4
B-out
4-bit Subtractor
B-in
B0 =0
D3 D2 D1 D0
Difference Output D
X2
Y2
B2
X1
Y1
B1
X0
Y0
B4
B-out Full
B-in
B-out
Subtractor
B-out Full
B-in
B-out
Subtractor
B0 =0
D3
D2
D1 Difference output D
D0
C4
C-out
4-bit Adder
S3 S2 S1 S0
C-in
C0 = 1
D3
D2 D1
D0
Difference Output
Binary Multiplication
Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier. y Ex. (unsigned)
y
X3 X2 X1 X0 x Y3 Y2 Y1 Y0 X 1101 multiplier (4 bits) __________________________ ------------------X3.Y0 X2.Y0 X1.Y0 X0.Y0 101 1 X3.Y1 X2.Y1 X1.Y1 X0.Y1 0000 X3.Y2 X2.Y2 X1.Y2 X0.Y2 X3.Y3 X2.Y3 X1.Y3 X0.Y3 1011 1011 P7 P6 P5 P4 P3 P2 P1 P0 --------------------10001111 Product (8 bits)
1011
multiplicand (4 bits)
_______________________________________________________________________________________________________________________________________________
array of n-1 n-bit adders where is adder is shifted by one position. y For each adder one input is the multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits.