Layout Reference Guide

Layout Class 4 reference book
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Layout Class 4 reference book

Global teamwork
Use booklets from analog layout class 2 & 3 for a reference guide
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When asked this riddle, 80% of kindergarten kids got the answer, compared to 17% of Stanford University seniors. What is greater than God, More evil than the devil, The poor have it, The rich need it, And if you eat it, you'll die?
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1.) capacitors 2.) resistors 3.) running an LVS JOB procedure 5.) how_to_create_pcf_file 6.) how_to_calc_res_length 7.) how_to_calculate_chip_size by hand, and if shrunk % is needed 8.) how_to_prune_multiple_nets 9.) how_to_run_block_parasitic 11.) APR chips 12.) how_to_use 13.) texted opens 14.) how_to_use match_by_property = TRUE detect_permutable_ports = TRUE
15.) how_to_use_snapshot 16.) unix_basic_commands 17.) How do I copy one cell from one library to another 18.) How do I reference a td library? 19.) How do I stream in a GDS file from the UNIX command line. 20.) how to do an XOR
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21.) guard ring creation capability for 160k 22.) Database Flow-sheet 23.) Derivative Hierarchy Checklist 24.) black box 26.) shuttles KEITH/ TIA 27.) multiple powers 28.) swappable_ports 29.) flatten files 30.) standard cell work 32.) master cells 33.) Layout extraction errors 34.) Fill program 35.) Mask Layers 38.) RIN 39.) extent box coordinates 40.) how to run list cells 41.) unused cell program
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42.) hidden cells program 42.) .cds.lib 42.) how to use name checker 42.) explode and flatten program 43.) step by step through the stream out check list for rev A0 44.) step by step through the stream out check list (quick check for IDC chips) 45.) how to use restrict_merge_series=false
46.) how to exp. Enlarge via cell in one shot, if via cell was exploded 48.) how to use vi 49.) how to substantiate a cell instance into your library 50.) technology file what is it, and how to use it 52.) How to open a zip file 53.) How to print a .pdf file 55.) what do you do if you have technology file issues? 56.) how to run shortest path to find shorts 57.) macro structure format 58.) how to create a iss netlist
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CAPACITORS
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CAPACITORS
here is a general rule, the higher layers you go in a process the less noise from the caps,
example; TSMC has a metal 3 metal 4 cap, it is
way up the layers near the top, so there is little noise.
substrate caps:
are very noisy because they go down to the substrate, in layout keep them away from sensitive analog devices and nets. Substrate is the lowest layer in processing
poly1/poly2 caps:
these caps are not as noisy and can be close to analog circuits. If one of the plates go to ground, it is still not as noise as a substrate cap.
Think of capacitors as a storage tank of charge, the bigger the more charge
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CAPACITORS TOP PLATE BOTTOM PLATE
This is a metal 3/4 cap, so the top plate is the highest layer, in TSMC metal 4 is higher then metal 3, so mtl 4 is the top plate, mtl 3 is the bottom plate
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CAPACITORS finding area

so how do you determine the area of a cap?
If you have to do it by hand here is the math; take the distance in the (x) times the distance in the (Y)so (x) X (y)=area
Go to the microchip utilities button and hit it, go down to were it says area and hit it; then click on the edge of the shape you want the area of; them look in your window and it will say, AREA=218.8551
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reading the schematic for a cap

Notice the m=20; that means place 20 of that size cap down in the layout.
This is the total area of the one cap, then place it 20 times
This is metal options
This is a probe pad
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reading the schematic for a cap
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Capacitor Matching
10
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RESISTORS
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RESISTORS
A resistor is an electrical component that resists the flow of current. The electrical resistance is equal to the voltage drop
across the resistor divided by the current that is flowing through the resistor. Resistors are used as part of electrical networks and electronic circuits. In general, a resistor is used to create a known voltage-to-current ratio in an electric circuit. A resistor is an electronic mechanism that is used to control electrical current through the use of electrical resistance. Resistors limit the flow of electrical current so that higher incoming voltage is reduced to a lower one that the component uses to operate. Electrical resistance or the resistance value, which is the ratio of voltage to current, is measured in ohms or megohms, which is the equivalent of 1,000,000 ohms. The higher the ohms or resistance value, the lower the voltage of the electrical current will be. LAYOUT
TYPES of RESISTORS
There are two types of resistors, fixed and variable. Fixed resistors have a fixed resistance, while variable resistors have an adjustable resistance value. Variable resistors are quite common. They are as familiar as a knob to control volume or brightness on a television set, or a temperature control knob on a heater.
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RESISTOR LAYOUT
13
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RESISTOR LAYOUT
14
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Matching Resistors
15
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RESISTORSRESISTORS-LAIED OUT
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how to run an LVS JOB

1.) make an hspice netlist, from the schematic 2.) make an command file exp; echo ram.hspice > ram.cmd 3.) run avanti_netlist exp; avanti_netlist --150k ram.cmd --150k this creates 2 files you will need to run LVS .iss & .eqv exp; ram.iss & ram.eqv 4.) submit your LVS run 5.) check your LVS run
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pcf_file
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how_to_create_pcf_file
The PCF file is a pad coordinate file created when you run the dump_pads program. It is now necessary to make the PCF a controlled document so that all those who need access to this information have one accurate source. A PCF file needs to be created for each product on a given mask set. Only one PCF controlled document should exist for each product unless the pads are moved or the die size changes. In this case per SPI-41002 the mask name should change. If historically this is not the case then a second PCF file will be created for document control and will be a rev of the first. All PCF files that are created prior to streamout are of course preliminary. Do not give or email a final PCF file to anyone accept document control. Once the final PCF file is created at streamout do the following to make this a controlled document:
1. Run bond on each derivation a. requires pad text on all pads. b. requires a triangle drawn on layer sd_align, same orientation and location as the derivation name. c. requires ext box drawn.
View the layout derivation example DEAG1 then when done making the pcf_file for it, do the next ones example DEAG2
the next pages are step by step on how to do pcf_files
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How_to_Create_a pcf_File
2. Run bond on each derivation-Select Synopsis Tools, from the pull down menu, click on Run Hercules Verifacation. A new window will open: fill out database name and derivative name of chip. Select long Queue, click type of process, New Deck and Bond then OK.
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3. In your Issbatch location, you will now have a directory with the database name and under this there will be a directory with the derivative name, under this there will be a directory called bond. In the bond directory there will bond file with a .gds extension.
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4. Stream data in: From the CIW pull down menu click on importanother pull down will appear. Click on stream, under input file, enter the path to your issbatch area where the bond_derivative.gds file is. In the library name space, enter the derivative name_bond. This will put bond_derivative.gds under this dir. Now click OK, when it is complete popup will appear saying it is done.
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5. In the library manager, there will be a new library derivative_bond. Open the derivative_bond layout.
Pads are along the white edge pads
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6. From Microchip Utilities pulldown, select Coordinates Utilities Pad Coordinates. A window will popup, select the right process, Mode- preliminary to let the engineer know if the pad locations will work, and final for when it is streaming out. Enter the mask name and mask rev. Then OK. There will be a PCF-mask name rev name.txt created in the virt area. 7. Run dump_pads on each product for a given mask set, or copy the PCF output for each product, being sure to edit the mask name in the header of the file.
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How_to_Create_a pcf_File, continued

8. Obtain the latest version of the general purpose change notice from chipnews. It is FRM-00008. Filling out form as follows: a. Reason A7BE1, Pic16c717 bond pad coordinate file. * note: use your mask and product name. b. Revision Notice - Check this box c. Effect on Manufacturing Cost: No d. Effect on Data Sheets: No e. ROM Code: No f. QA QB NO - Check the No box g. Disposition of Inventory - No h. Finished Goods - none i. Strat. Inventory - none j. Sample Center - none k. Work In Process - none l. Effect On Production Choose No Obsolesce of Materials or Parts m. New Release - Check this box n. Specification or Drawing Number: PCF-A7BE1 Note: Use your mask name o. Current Revision: Leave blank, this is not applicable
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Filling out CN, continued p. Description (Details)
How_to_Create_a pcf_File, continued
If this is a new Rev a0 database, you may leave this section blank. If this is the first controlled document PCF file created from an existing revised database, you may want to note the following: This bond pad coordinate file was created from the A7BE0canb2 database. Neither the bond pad positions nor the die size has changed since the A7BE0cana0 database was created. Note: Be sure this is the case q. Three approval signatures are required: Design Engineer Layout Designer Mask Making r. Sign the signature box indicating who prepared the CN. 5. Attach a copy of the PCF file to the CN and obtain the signatures. 6. Email an electronic copy of the PCF file to Diana Salisberry in Document Control. This electronic copy must be cut and pasted into the original email, not an attachment. Deliver the signed hard copy to Document Control.
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how_to_calc_res_length
If
you are on the layout and going to tell the engineer the number to put on the schematic. Get area of res layer Get width of res layer drawn length = area / width
calculated length = drawn length - ( width * bends ) / 2 This is because when you draw a bend you actually lose half the resistance. If your schematic has a length that you must match drawn length = request length + ( width * bends ) / 2 This is because you must draw the resistor longer for every bend that you have to get the same resistance.
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how_to_calculate_chip_size
dump_pads calculates the size of your chip based on your extent_box. The number is specified in millimeters. To calculate this number by hand you use the following steps. First you must measure your extent_box. You will have an x and a y number that is in microns. If you are working on the 77k process you must multiply these numbers by .90. This is because the process is shrunk at mask making. If you are working on the 120k process you must multiply these numbers by .75. This is because the process is shrunk at mask making. If you are working on the 150k process you must multiply these numbers by .50. This is because the process is shrunk at mask making. If you are working on the 160k process you must multiply these numbers by .40. This is because the process is shrunk at mask making. The actual size of the chip also includes the scribe line which is a different size for each process as described below. process 57k/77k skinny 77k 150/160 scribe x size 142 118 117 scribe y size 144 118 117 117 140
skinny 120/121 117 90k/120k/121k 136
You must add the x scribe size to your x number above and you must add the y scribe size to your y number above. Remember that the scribe numbers are never ever scaled.
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how_to_calculate_chip_size
The following example demonstrates the calculations for 120k by hand: 1) Measure your extent_box 1000u in the x direction 2000u in the y direction 2) Multiply by the scale factor 1000u * .75 = 750u in the x direction 2000u * .75 = 1500u in the y direction 3) Add the scribe size 750u + 136u = 886u in the x direction 1500u + 140u = 1640u in the y direction To convert microns to millimeters move the decimal point over three positions 886u is the same as .886mm 1640u is the same as 1.640mm To convert microns to mills divide by 25.4 886u / 25.4 = 34.88 mils 1640u / 25.4 = 64.57 mils
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prune
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how_to_prune_multiple_nets
After some investigation, it is possible to prune more than one net at the same time. You just need to know the correct syntax to put on the line. If you are pruning one net, just type the net name: i.e. ASIGNAL If you are pruning two nets, you type the first name, two ", and the second name with NO SPACES. i.e. ASIGNAL""BSIGNAL Notice that there are no quotes at the beginning or end or the example. For more than two nets, just keep separating each signal name with two ", and no spaces. i.e. ASIGNAL""BSIGNAL""CSIGNAL
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how_to_run_prune
To run a prune you must have the metal or poly2 text at the level that you are going to prune the net at. To check this, use vlvl 0 to see if the text you are going to prune for is visible. You cannot have any shorts on the net that you are pruning otherwise your output will be empty or incorrect.
The command to run the prune is iss_verify with the p option.
When you are trying to prune vdd! or gnd! you must type vdd\! or gnd\! This is because ! is a special character. Prune only works on one net at a time and creates a prune_NET.db database where NET is the net name you have specified and the database location is based on the location of the original database. ie. if you pruned d:jude.db for net qrt a d:prune_qrt.db database would be created. Below is an example of a prune iss_verify run: Would you like to do an [a]ntenna, [b]ond, [d]rc, [p]rune, [l]vs, or [c]ompare run? : D efault [l] : p Please enter the pathname to the library. (Do not include layout) Default [/home/data2/B5AC0cana/iss] : Please enter the library name. Default [B5AC0cana.db] : Please enter the structure name. Default [chipB5AC0] : Please enter the process to use ( 121000, 120000, 120000ds, 90000, 77000 ) Default [121000] : Do you want to use the new process deck. [y]es or [n]o : Default [n]o : Please enter the layout explode/flatten file. Enter space to reset default. Default [] : Run lvs or prune with wells connected. (true, false) Default [TRUE] : Run lvs with parasitic extraction. (true, false) Default [FALSE] : Please enter the net name to prune. Default [vdd\!] : rsh euryale 'cd /home/euryale/lhigh/issbatch/B5AC0; echo setenv LVS_KEEP_WELLS TRUE\; se tenv PARASITIC FALSE\; setenv EXTRACT TRUE\; sed \< ~library/tech/121000/prune.vc \>\! /tmp/prune.$USER.vc -e 's/NET_TO_FIND/"vdd\!"/g'\; vericheck -b chipB5AC0 -i B5AC0cana.d b -o prune_vdd\!.db -p /home/data2/B5AC0cana/iss /tmp/prune.$USER.vc \>\! chipB5AC0.plo g | /pkg/batch/bin/batch -v verify_long'
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Select Synopsys Tools, from the pull down menu. Click on Run Hercules Verification. A new window will pop up. Input needed information. Select Under Nets To Prune Input the net names that the Engineer wants. To pruning two nets, you type the first name, "", and the second name with NO SPACES. i.e. ASIGNAL""BSIGNAL For more than two nets, just keep separating each signal name with "".
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In your Issbatch location, you will now have a directory with the database name and under this there will be a directory with the derivative name, under this there will be a directory called prune. In the prune directory there will prune file with a .gds extension.
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Stream data in: From the CIW click on file. From the pull down menu click on importanother pull down will appear. Click on stream, under input file, enter the path to your issbatch area where the bond_derivative.gds file is. In the library name space, enter the name that will identify the type of prune file. This will put spencen_prune.gds under this dir. Now click OK, when it is complete popup will appear saying it is done.
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How do I prune a net?
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Execute "Streamout for Hercules" from the Avant! Tools menu. Under the "Type of Run" field, change it to "Prune". Type the net name you want to prune in the next form, and hercules will run. When the results are complete, you will have a stream file in the issbatch area where the prune was ran. You will need to stream in this file into a NEW LIBRARY! It is important to stream it into a completely new library so that none of your existing data will be overwritten.
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how_to_prune_a net
Select Synopsys Tools, from the pull down menu. Click on Run Hercules Verification. A new window will pop up. Input needed information. Select Under Nets To Prune Input the net name the Engineer wants.
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how_to_prune_a net
Stream data in: From the CIW click on file. Then from the pull down menu click on importanother pull down will appear. Click on stream, under input file, enter the path to your issbatch area where the bond_derivative.gds file is. In the library name space, enter the name that will identify the type of prune file. This will put spencen_prune.gds under this dir. Now click OK, when it is complete popup will appear saying it is done.
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block_parasitic
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how_to_run_block_parasitic
Select Synopsys Tools, from the pull down menu. Click on Run Hercules Verification. A new window will pop up. Check lvs_ww, New Deck, process type for 150k needs to be mgg150k, Queue type, fill in Schematic Netlist and Equivalency files, and make sure that Star RCXT is checked. The Star RCXT creates a file in the milyway directory. 1. The block/chip must be lvs clean, and Star RCXT needs to be checked.
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2. When lvs is clean, run name_checker.pl from the lvs run directory. View the compare.out file using the more command. Check for name mismatch at the top level.
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There are multiple options you can choose to create an hspice netlist from a layout. /* This OPTION does not work with the current release of hercules */ If you want the layout netlist to have the same names as the schematic netlist, you first have to get a clean lvs run on the block that you are interested in. /* This is the only OPTION supported */ If you do not mind seeing net names such as NET_101, then the above lvs is not necessary.
Too generate a parasitic netlist run:

avanti_hercules Choose lvs for the following type of run prompt Would you like to do an [a]ntenna, [b]ond, [d]rc, [p]rune, [l]vs, or [c]ompare run? : Default [l] : l Choose your queue, library path, library name, block name, process, new or old deck, and flatten file as you would for any other lvs run. For the question Run lvs with parasitic extraction. (true, false) Default [TRUE] : Select True This disables the compare part of the lvs, and creates an hspice netlist instead of the .net file used for compare. You have two options of the type of parasitic capacitors that can be extracted. Output lumped capacitance in spice netlist. (true, false) Default [FALSE] : If you answer true, you will get a lump capacitor netlist which will give you one capacitor for every net in the netlist. All of the capacitors associated with that net are summed together and tied to ground. If you answer false, you will get a node to node capacitor netlist. In this case you may have hundreds of capacitors attached to a net. If a net is routed in metal2, every time it crosses over a metal1, poly2, ndif, or pdif polygon, a node to node capacitor is created. This option should only be used on small blocks that are very critical to simulate accurately. Lumped capacitors should work for the majority of circuits. /* This OPTION does not work with the current release of hercules */
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2. Select Synopsys Tools, from the pull down menu. Click on Run Star RCXT. A new window will pop up. The database and derivative names are already there, and so is the process info. The path to the Hspice Netlist file needs to be entered. The Run Type, Netlist Format, Poly1, XREF, INSTANCE, and Corner info will be given by the Engineer. When Star RCXT is complete. There will be a new directory in the issbatch area under the database and derivative name called starrcxt. Do a more on the star.log to make sure that Star RCXT completed. When it is done let the engineer know.
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Use net cross reference from previous lvs run. (true, false) Default [TRUE] : If you have run the above mentioned lvs, then you can choose true here. Your layout names in the hspice netlist will be identical to the names in your schematic. This makes simulating the netlist easier for the engineers. If you have not run an lvs, you must answer false to this question. If you answer true, the extraction will fail with a warning that top level block not found. The netlist produced will be in block_name.sp. It will not contain a subckt definition for the top block. The engineer simulating the netlist is responsible for adding this line. Some side notes to make the process smoother. If you have used cont, poly, or via cells, explode them in your flatten file. These subckts add to the complexity of the netlist and can cause bad results. After you run the parasitic netlist generation, look at all the subckts that have been created in the netlist. If there are any that should not be there, add them to your flatten file and run the parasitic run again. The only process currently supported is 120k. As soon as a need for the other processes is determine, we will add this capability. If you only have analog pwell in a block, the substrate will not be hooked to ground. To get around this issue, draw a small piece of pwell that meets drc specs and label it gnd. Since pwell is not a mask layer, and all of substrate is technically pwell, this will not hurt the layout design. This pwell will tie to the substrate and take care of the lumped caps and ppnwd diodes going to a ln_NET_1 type of net. Finally, if you have a problem, contact CAD immediately. We should be able to help get the extraction back on track.
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how_to_run_parasitic
Once a prune has been run you will have a pruned database. It will be in the same disk that contains the database that you ran the prune on. The name of the database will be $USER_prune_netname.db. To find out the parasitics of this prune net you must do the following. You must label the net in the pruned database. You must also create a flatten file that flattens the database on extraction. Now you are ready to find out the parasitics of the pruned net.
Below is an example of a parasitic avanti_hercules run:

Would you like to do an [a]ntenna, [b]ond, [d]rc, [p]rune, [l]vs, or [c]ompare run? : D efault [l] : l Please enter the pathname to the library. (Do not include layout) Default [/home/data2/B5AC0cana/iss] : Please enter the library name. Default [judiscak_prune_clk.db] : Please enter the structure name. Default [prune_chipB5AC0] : Please enter the process to use ( 121000, 120000, 120000ds, 90000, 77000 ) Default [120000] : Do you want to use the new process deck. [y]es or [n]o : Default [n]o : y Please enter the layout explode/flatten file. Enter space to reset default. Default [] : flatten Run lvs or prune with wells connected. (true, false) Default [TRUE] : Run lvs with parasitic extraction. (true, false) Default [FALSE] : true The output of this run is a .sp (spice file). It will contain many capacitors. You should look for the capacitor that is hooked up to the net you labeled. This is the the lumped sum capacitance to ground that the net sees. You can use this in a spice or verilog simulation run.
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APR blocks
Automated Place & Route (APR)
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APR chips
Automated Place & Route (APR) process flow. The basic process: Inputs: The APR flow supports structural (or gate level) Verilog netlists, with the most basic building blocks (or leaf cells) being Standard cells from our libraries, Custom Layout blocks (Hard Macros in APR-speak) or Pads from our libraries. The APR process is the first point in the flow where the physical world and the logic-design world meet. Since the tool does (and should) not assume anything, we have to tell it implicitly what we want. The Physical layout is fed into Apollo as GDS data. This data is converted to a connectivity view inside the Milkyway database. This connectivity view contains pin target and access information, obstructions for the block as well as logical data associated for this block as required. Since GDS data cannot contain connectivity, it is not possible to use a custom database as a starting point into Apollo. For pad-based layout, the required pin out and/or pin order and die size, have to be specified. For building blocks, we need to specify the dimensions and for blocks with polygon-shaped extents (Called Rectilinear blocks), we need definitions of the sizes of the sides. The pin information can be specified in a variety of ways: From no specification through exact positioning and layer specification of each pin. For synthesized and/or timed designs, the list of inputs and required specifications gets more complex. Since the design intent in synthesis is more than just interconnect of building blocks, the other IP outside the netlist, is transferred by the clock tree nets, timing constraints, clock specification and synthesis data and synthesis libraries and list of operating conditions.
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APR chips
Automated Place & Route (APR) process flow. The basic process: The primary output is a GDS file. This file contains instantiations of all the macros and cells called for in the design. The interconnect is very often the only explicit information in the GDS file The macros and the Standard Cell information should be referenced from the Custom layout area or the standard cell layout library. General statistics for the design includes cell counts and usage, areas and interconnect distribution as well as utilization numbers. For simulation or Timing Analysis (TA), an SDF output can be generated, as well as many different parasitic formats, including Standard Parasitic Extraction Format (SPEF), Detailed Standard Parasitic Format (DSPF) and SPICE-type RC-interconnect capacitance. For designs requiring Gated Clock Tree Synthesis (GCTS), a new netlist for the design will also be generated. * Major issue: Every pin on a verilog module MUST have a one-to-one correspondence to a matching layout pin. Remember Verilog is case sensitive and pin abcd is NOT THE SAME AS pin Abcd. Bus pins in Verilog are labeled as BusMember[n] and must be labeled in layout as such.
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* Custom Layout (Hard Macros) For every hard macro used in the design, the APR requirement is that the module 1. must have all internal connections called for in the schematic, connected internal to the block 2. must have an identical layout pin to the each verilog port in the netlist. This includes case sensitive names and correctly named bus notation. For many modlib cells, these issues are not taken care of automatically and another "dummy" level of hierarchy may have to be added to correct the cell. 3. Must have accessible pins on the labeled shapes in the layout. Note that the APR process uses a simplified DRC deck that does not allow the flexibility for routing inside macros that the custom designer could utilize. In general, it is a good idea to have all pins directly accessible from at least one side. It may also be very helpful if pins can have stacked vias to allow access on different metal layers if the block is rotated. Poly routing is generally not supported and is DRC error prone inside macros. In general it is therefore advisable that no interconnect pins be labeled on Poly only. To standardize the process of using hard macros, the following should be adhered to as far as possible: * Define the list of macros in the file macs.map (See description above) * Each of these macros must be instantiated inside a versioned GDS file indicating the top cell block they are used in: in the format CUSTOM_CELLS_<top_module_name>_v3d2 with a top cell called CUSTOM_CELLS This indicates that the GDS file is at Major revision 3 and minor revision 2. (i.e v3.2) To build the CUSTOM_CELLS top level cell, generate a file (macs.lis) with a macro name per line (based off macs.map see above) . Open a new cell in lplus and the type the following in the command window (CIW) : pla "macs.lis" "layout"
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This will generate the CUSTOM_CELLS layout for all the modules to be used. * To generate the corresponding schematic for this layout, do the following: Open a new cell in opus and the type the following in the command window (CIW) : pla "macs.lis" "symbol" This will generate the CUSTOM_CELLS schematic for all the modules to be used. Since these modules are connected, the rules check for verilog netlisting needs to be modified: Check->Rules Setup and change all errors to ignores or warnings. Check & Save the design. The verilog netlist generated for this design will be used to verify schematic to layout pin correspondence. Check layout vs Schematic pin data: Catenate all module verilog files into a single file & run pin checking script: cat <Path to CUSTOM_CELLS verilog netlists>/*.v > all_macs.v Run Milkyway to extract pin connection information ( You may need a simple script for this):
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reference a library
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how to reference a library

Go the tools button and a pop up window will popup;
Then hit the library path editor button, then this will pop up;(see next page)
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library path editor
This tells you how to put in the name of the library
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Now we added to new library look here at what it is saying;
The reason the error About it being a bad Path showed up was It should have said tsmc_018_prims The s was missing This was the new added library
hi
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Now we added to new library
Now the library shows up in The design manager

hi
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detect_permutable_ports
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how_to_use_detect_permutable_ports
The new hercules sometimes reports that it detected permutable ports but the permutable ports option is not enabled. To save time, no process is done. To solve this problem you must put the permutable option in your .eqv file on the equiv point that failed. Exp.
equiv a = a {detect_permutable_ports = TRUE}

Do a compare run. The block will then tell you the permutable ports. It is in your best interest to label these ports the same as the schematic, and then pull the above option out of the equiv file. Now run another compare job and make sure you are still clean. Labelling your ports always eliminates the swappable problem listed above. YOU WILL USE THIS MOST OF THE TIME WORKING WITH ARRAYS
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DETECT_PERMUTABLE_PORTS Port Swappability

The major difficulty hierarchy presents in the comparison stage is determining port swappability of sub-blocks. There are two types of swappable ports: " Independently swappable ports are logically equivalent ports that can be inter changed without affecting their function within the block. For example,any inputs of an NAND gate can be swapped without changing the function of the gate. " Dependently swappable ports rely on their functional relationship within the block and, therefore, cannot be separated from one another. We go through a simple explanation of each in this chapter. Detecting Swappable Ports The LVS COMPARE option offers an advanced algorithm for detecting and handling the comparison of swappable or permutable ports. Placing the DETECT_PERMUTABLE_PORTS command in the COMPARE section of the runset allows you to have swappability rules applied and extracted automatically. In the AND-OR-INVERT cell, A cannot be swapped with C unless B is swapped with D, thus demonstrating dependent swappability. In contrast,the independently swappable ports, A and B, are interchangeable, as are C and D.AND-OR-INVERT Hercules has algorithms built into the code to determine the most complex swappability cases, but, in some flows, the designers might want to restrict what blocks are allowed to have swappable ports. You should set DETECT_PERMUTABLE_PORTS to TRUE in the COMPARE options section,
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You should set DETECT_PERMUTABLE_PORTS to TRUE, This type of schematics you will need detect_permutable_ports = TRUE
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This is an example of what it will look like when you need detect_permutable_ports = TRUE, AND YOU DONT HAVE IT IN THE .EQV FILE when I hit the add button this apperars, so what is this saying?
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This is an example of what it will look like when you need detect_permutable_ports = TRUE, AND YOU DONT HAVE IT IN THE .EQV FILE When I ran bytex2 by it self it was 100% clean, but when I ran this run at array256k level it now tells me there is a problem in cell bytex2; you can not call any of these blocks clean untill all of them are clean. The way we find out what is wrong here is to 1.) click on block with the red circle bytex2
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This is an example of what it will look like when you need detect_permutable_ports = TRUE, AND YOU DONT HAVE IT IN THE .EQV FILE The way we find out what is wrong here is to 1.) click on block with the red circle bytex2 2.) bring up the equivalence summary file under the View button. It will give you the file below. There are two ways to see From this what is needed. 1.) it is telling you (port swap problem) when you see that you need detect_permutable_ Ports = TRUE in your ,eqv file by that name, also read this below it is telling you, you need that statement in the .eqv file.
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This is an example of what it will look like when you need detect_permutable_ports = TRUE, AND YOU DONT HAVE IT IN THE .EQV FILE So lets add them to the .eqv file and rerun the top level of the array.
Old .eqv file without statement in it This was NOT CLEAN
This is the CLEAN .eqv file Notice the statement
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opens
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texted opens
When I ran the top level vpp_reg, it Came back and said I have Layout extract errors, this is a lower block in the chip. Texted opens are ok in lower blocks But it helps as you move up not to have them. So I Hit on the layout extract errors and this box pops up. This says I have 3 texted opens, I looked at the layout And all 3 are power, gnd and vdd opens. Next I look at the file vpp_reg_LAYOUT_ERRORS, to See this file hit the view button, notice 3 violations, Texted opens, they can be fixed by hooking up the Powers inside the cell, this is preferred, at times we Lets them go and make sure they are hooked up at the Next level in the layout. the only texted opens you will allow here are power ground opens
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Match_by_property = true
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When you hit the Add button You get this pop up: When you hit this you get The Property mismatched Then hit this and all the cap Sizes come up as wrong Sizes because the tool is confused
The tool has a problem with lots of caps in the same block, it gets confused about sizes. The way we fix this is by Putting in the .eqv file this statement Match_by_property = true See next page for example
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This is the .eqv file. This .eqv Had lots of property Mismatched devices, notice This line in the .eqv file Now noticed what we added To make the property Mismatched devices go Away. The tool has a problem with lots of caps in the same block, it gets confused about sizes. The way we fix this is by Putting in the .eqv file this statement Match_by_property = true
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snapshot
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Go to your working directory
how_to_use_snapshot
cd virt
Then cd into your project directory in this case D5AB0canc0

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Go to the directory
how_to_use_snapshot
Your working area; this case chipD5AB0
Then cd into the cell you are wanting a snapshot of, in this case cap_100
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how_to_use_snapshot
cd into layout, the file you are interested in is layout.cdb
Then cd into .snapshot
This is the snapshots taken of this directory, the days are the days a snopshot was taken, the times are of the current day. This is saying is replace the layout directory for cell cap_100 with its snapshot from 8:00pm . The cd into the time of the snap shot you need.
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how_to_use_snapshot
cd into the time you want your snapshot taken fromlayout.cdb in this case 20:00
Then copy the snapshot to the corrupt cell and replace it
Note: the -r was needed because this was a directory, the . says place it here. So what This is saying is replace the layout directory for cell cap_100 with its snapshot from 8:00pm . I did that and it told me there was no change in the directory. That told me LAYOUT nothing had changed between the two. My cell was not corrupted so I did not replace it.
unix_basic_commands
mkdir name lpq -Pname cp file1 file2 mv file1 file2 pwd df . hostname ~username ls & ctrl z fg bg lpr file enscript file man function | - will create a directory of the name specified - will view the different plot queues valid names are: lws, lwz, lwt, hp650c, vplot, v44c - copies file1 to file2 - moves file1 to file2 - tells present working directory - tells disk current working in - tells machine logged into - finds username's home - lists current directory - puts job in background - suspends job - puts suspended or background job in foreground - puts suspended job in background - prints file without any formatting - prints file with numbering, header, wraparound, date... - gives help on the function specified lprm -Pname job# - will remove a job from the queue
- pipe that concatenates two commands together ls * | more
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unix_basic_commands
> tab - redirection to a file ls * > pig.dat ( look at pig.dat to see the listing ) - hitting the tab key will expand your command line ls 9702<tab> might expand to ls 97020cana0
ctrl d - if hitting the tab causes a beep more than one expansion is possible hit the control key and d and it will list the possible expansions ls 9702<ctrl d> might list 97020cana0 97021cana0 ( both are legal expansions )
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u How do I copy one cell from one library to another

When you stream data into an existing database that is attached to a technology file, you need to make sure that the option to ignore undefined layer purpose pairs is set. If it is not set, you will get an error message regarding the inability to open the techfile in edit mode. If you ignore undefined layer purpose pairs, then the streaming tool has no need to write the techfile. The default setting should have this option set, so you shouldn't have to do anything special to stream data into an existing database. There are a copy ways of doing this; note they must use the same technology files 1.) go to your tools button 2.)then hit the layout manager button
3.) the layout manager window will pop up, like the one below;
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There are a copy ways of doing this; note they must use the same technology files 1.) go to your tools button 2.)then hit the layout manager button 3.) the layout manager window will pop up; notice libraries C5AV0canc0_LH and C5AV0canc0_new Lets say I want to copy a cell from C5AV0canc0_new into the C5AV0canc0_LH library.
4.) go to the cell you want to copy in the library manager window, click on the library it is in, then the cell name, then the layout button
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There are a copy ways of doing this; note they must use the same technology files
1.) go to your tools button 2.)then hit the layout manager button 3.) the layout manager window will pop up; notice libraries C5AV0canc0_LH and C5AV0canc0_new 4.) go to the cell you want to copy in the library manager window, click on the library it is in, then the cell name, then the layout button; then hit the right click button on your mouse, then click on copy button; this pop up will appear;
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There are a copy ways of doing this; note they must use the same technology files
this pop up will appear; What this is saying is, you are copying from Library C5AV0canc0_new, a cell called larry in layout; Into the Library called C5AV0canc0_lh, the same cell larry in layout;
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There are a copy ways of doing this; note they must use the same technology files If the library is in a different locations, just bring up your library path editor under your tools button and add it in and do what is on the pages in front of this one and copy it in.
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How do I reference a td library?
All of the td libraries are located under ~library/dflib/virtuoso. Each project can point to at MOST two technology libraries, one for 150k and one for all other processes. If you are using a 150k td library, it must be defined as follows: DEFINE 150_td_lib /home/users/library/dflib/virtuoso/150tdcel_a If you are using any other td library, it should be defined like this: DEFINE td_lib /home/users/library/dflib/virtuoso/120tdcelep_a It is important to note that there are only two valid technology library names, 150_td_lib and td_lib.
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How do I stream data into an existing Virtuoso database?

When you stream data into an existing database that is attached to a technology file, you need to make sure that the option to ignore undefined layer purpose pairs is set. If it is not set, you will get an error message regarding the inability to open the techfile in edit mode. If you ignore undefined layer purpose pairs, then the streaming tool has no need to write the techfile. The default setting should have this option set, so you shouldn't have to do anything special to stream data into an existing database.
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This is a two set process. Step 1: 1. Open layoutPlus (lplus)
How do I stream in a GDS file from the UNIX command line.
2. From the CIW, open the stream in window. File --> Import --> Stream... 3. Fill in the form with the necessary data. 4. Type a file name in the "Template File" field and remember where you put it. 5. Click the "Save" button beside the "Template File" field. 6. Click "Cancel" to cancel the Stream in form. Step 2: 1. From the UNIX command line, cd to the directory where the cds.lib file resides. 2. Type the following command to stream in pipo strmin <template_filename> 3. Look at the log to make sure the stream in was successful. <template_filename> is template file created at item 4. in Step 1. This file will contain the path to the GDS file, technology info, library name, log file, etc. The template file can be copied, hand-edited, and reused.
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uLets say I have a .gdsii file and I need to stream it in. How do I do this?
Here is the file we want to stream in. This is a example only;
1.)Then you need to stream it in to; How do you stream it in? go to your file button; 2.) then to import button 3.) then stream button (the pop up below will show up);
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What this is saying, stream in the .gds file at this location. Put the input file name in this box; /home/users/issbatch/lhigh/c5av0/c5av0/fill/lhigh_fill.gds
This is where you put the name of the new library you are streaming in
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This will pop up if your stream was successful
Notice below the new library is now in the design manager window
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how to do an XOR
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how to do an XOR
1.) go to system tools button (pop up will show up 2.) hit run hercules verification button (this form will pop up) 3.) then hit xor button; the xor1 does a copy of the new database you want to be compared the xor2 does a copy of the old database you want to be compared, run xor1 and xor2 not at the same time
When you run xor between databases make SURE your database name is the same so the output information goes to the same place from xor1 and xor2.
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3.) then hit xor button; the xor1 does a copy of the new database you want to be compared the xor2 does a copy of the old database you want to be compared, run xor1 and xor2 not at the same time Cell being comparied library cell is in database to put both xor in
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This tells me it ran
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1.) bring up the old database that you want to (xor) against 2.) go to system tools button (pop up will show up 3.) hit run hercules verification button (this form will pop up) 4.) then hit xor1 button; 5.) this will create a directory (xor/)under your project area; exp; /home/users/issbatch/lhigh/c5av0/c5av0/xor
6.) now bring up the new database you want to be compared with the old database 7.) go to system tools button (pop up will show up 8.) hit run hercules verification button 9.) then hit xor2 button;
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1.) bring up the old database that you want to (xor) against 2.) go to system tools button (pop up will show up 3.) hit run hercules verification button (this form will pop up) 4.) then hit xor1 button; 5.) this will create a directory (xor/)under your project area; exp; /home/users/issbatch/lhigh/c5av0/c5av0/xor
6.) now bring up the new database you want to be compared with the old database 7.) go to system tools button (pop up will show up 8.) hit run hercules verification button 9.) then hit xor2 button; make sure all the information above stays the same. It needs to put the xor2 results in the same place as the xor1 results.
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1.) bring up the old database that you want to (xor) against 2.) go to system tools button (pop up will show up 3.) hit run hercules verification button (this form will pop up) 4.) then hit xor1 button; 5.) this will create a directory (xor/)under your project area; exp; /home/users/issbatch/lhigh/c5av0/c5av0/xor 6.) now bring up the new database you want to be compared with the old database 7.) go to system tools button (pop up will show up 8.) hit run hercules verification button 9.) then hit xor2 button; make sure all the information above stays the same. It needs to put the xor2 results in the same place as the xor1 results.
10.) then go to the system tools button 11.) then hit start explorer DRC button note you must add the xor directory to the path below
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1.) bring up the old database that you want to (xor) against 2.) go to system tools button (pop up will show up 3.) hit run hercules verification button (this form will pop up) 4.) then hit xor1 button; 5.) this will create a directory (xor/)under your project area; exp; /home/users/issbatch/lhigh/c5av0/c5av0/xor 6.) now bring up the new database you want to be compared with the old database 7.) go to system tools button (pop up will show up 8.) hit run hercules verification button 9.) then hit xor2 button; make sure all the information above stays the same. It needs to put the xor2 results in the same place as the xor1 results. 10.) then go to the system tools button 11.) then hit start explorer DRC button note you must add the xor directory to the path below 12.) then the window below will pop up, all the above are changes between the two databases
how to view the xor changes
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LINE #17
To find out what layers have changed, all the layers in the box have changed. To find out what layers they are you need to go to cadweb, see below
You need to go to technology files, then hit the process you are using button, and all the layer Names and numbers will show up. Example above, array layer on data type 0 is layer number 39
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LINE #17
Below this states that there were 52 differences between old_a10_0 and a10_0. So What layer is a10_0? The _0 is the data type, to find out what a10 is you need to go to
technology files, then hit the process you are using button, and all the layer names and numbers will show up. Example below, find number 10/0, what layer is it? Poly 2, so ploy2 layer changed
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guard ring creation capability to 160k

I have added guard ring creation capability to 160k. This uses multipart paths. This functionality is only available with Cadence IC5.1.4 (If anyone is still using an older version, please get in touch with me or the Systems Administrator to get the links changed on your system) From a Layout window, choose Create --> Multipart Paths. Then F3 to bring up the Options Form. Choose the type of guard ring you require from the MPP Template drop down (on the top right) Then draw as if it is a regular path. The Metal and Contacts can be selected and chopped for routing purposes. The Active and Well are set to not choppable. For example "guardring_NDC" will give you N guard ring with double contact. If you want to set up a bind key add the following line to your ~/.cdslocal file. I used CTL-M in this example. You may pick your own key sequence. hiSetBindKey("Layout" "Ctrl<Key>m" "leHiCreateMPP()")
Please check this capability out and send me some feed back. I'll be working on tsmc_025emf, tsmc_018 and 200k in the future. I can create other combination if needed...
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Database Flowsheet
1. working in. You can use the "copy library" with options clicked on update instances of entire Library, or use copy wizard under the edit menu of the library manager. This may take a while if it's a large database.
1 of 2 Database Flow-sheet layout to the PAGE you will be Flow- necessary Create a layout/virt area if your lead engineer hasn't already done so. Copy database
2. Get from your engineer the macros, pad cell library, and standard cell library that you will be using in the project. Get the paths and add these paths to your cds.lib 3. If this project is to be apr'd , generate a custom cells gds that contains the macros thru lplus under the synopsys tools menu, then run Hercules verification with apr run type clicked on submit to your APR person. (Your custom_cells layout will contain macros used for the project. Just instance these macros in) 4. Generate a custom_cells.hspice off of your custom_cells schematic. You will need this to add to your toplevel.cmd file 5. Once you get a preliminary gds from APR it would be a good idea to run the following: * Listcells - Make sure you are pointing to the correct paths/revisions Listcells is your friend when it comes to database management. Flatten contacts, vias, M1M2 * Drcs Report any drcs caused by apr to the APR person This includes metal slot error, shorts caused by overshot of metal or any errors that you think may have been caused by the apr tool. Give x & y coordinates. * LvsFor the obvious reason-how clean is the layout
6. You may have several apr spins before you get a final gds. Once you get a final gds and the pads are stable, run a preliminary PCF. Submit a hard and electronic copy to Assembly. When you are streaming out, you will need to generate a Final PCF and give to Mask. Once Mask gives the "ok", then submit the Final PCF along with a General Purpose Change Notice to Document Control. Do this if this is an a0 product. 7. Create a toplevel_overlay cell and instantiate that into your toplevel cell. Your Overlay cell will contain additional edits (such as shielding, antenna diodes, rerouting of signals and guardrings) that you have to make at toplevel. We do this so that we will not lose any of those edits for future revision of the database.
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Database Flowsheet 8.
PAGE 2 Database Flow-sheet Make plots, prune plots. of 2 Flow- shielding? Check with engineer for critical signals and power grids. Width of signals,
9. If this is a derivative product, please follow the Derivative Hierarchy Checklist. LVS 1. You will need to add the following to your toplevel.cmd to generate your .iss and .eqv file. toplevel_CTS_mpg.v (get this from APR) custom_cells.hspice other verilog/hspice for outside foundry modules (EXAMPLE artisian_8Kx8_dphd_v10_2004q2v1.cdl, eth_10btphy_v1d1_analog10.hspice. You will need to ask the engineer where these files reside.) 2. If you have derivatives you will also need a .v file for each flavor (EXAMPLE - debf1.v, debf2.v and etc.) 3. To generate a iss and eqv file, type at the unix prompt avanti_netlist pz sn --tsmc toplevel.cmd pz sn = pad library = standard cell library
--tsmc = process Follow the streamout checklist for a successful streamout
Put together by Lupe Badilla
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Derivative Hierarchy Checklist

The Derivative Hierarchy Methodology only needs to be used if there are derivatives. Refer to the product DOS to determine if there is more than one product for the project mask set. Details on any point of this checklist may be found on CADWEB. q Base structure has been named with the all-uppercase, four-character mask name ending in 0 (zero), outlined in the DOS. Example - DYYY0. o Base structure contains only data, polygons, instantiations that are common to all product derivatives. o EXTBOX, a generated metal fill instance, maskright, copyright, and alignment triangle on layer "sd_align" have been placed in base structure. q Revision levels/scribe structures have been created: o For 120k and 121k place revision levels in base structure. o For 150k, 160k, 180k place two scribe structures in master structure. Use Microchip Utilities - Text Placement - Create Scribe Cell from its Virtuoso pull down menu to generate scribe structures. o Revision level/scribe structures carry the same five-character mask name as the base, plus the suffix "_SCRIBE" and "_SCRIBEG". Example: "DYYY0_SCRIBE" and "DYYY0_SCRIBEG". q Derivative structure has been named with the all-uppercase, four-character mask name with a different fifth numeral separating it from the others in its product set. Examples: "DYYY1", "DYYY2", "DYYY3". q Derivative structures contain: o An instance of the base cell has been placed at (0,0) inside derivative. o All derivative level layer data has been drawn on data types 3 and 4, or on layers: sd_align, option1, option2, option3, option4, and note. Text and pin text are always permitted on the appropriate layers. q Master structure has been named with the same five-character mask name as the base, plus the suffix "_MASTER". Example - "DYYY0_MASTER".
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Derivative Hierarchy Checklist

q Master structure contains: o An instance of all derivatives in its product set is placed in the master structure. Each derivative is placed one micron apart (measured from EXTBOX to EXTBOX) to avoid false density errors from DRC. o For 150k, 160k, 180k place generated scribe structure instance in master, as mentioned previously. o All global labels are placed at master level for LVS. q "Fracture Coordinates" program has been run from Virtuoso Microchip Utilities pull-down menu, and all errors have been cleared. q DRC has been run from master level, and all data type warnings occur at derivative levels of hierarchy only. Once the items on this checklist have been completed, the Lead Layout Designer is ready to begin the STREAMOUT CHECKLIST (FRM-47007-1). This checklist is provided as a learning tool, and should not be considered an official document. Please consult the CAD Development Dept. if you have any questions regarding the content of this checklist
Put togeather by Lupe Badilla
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master cells
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What is a master cell?

A layout structure containing a single placement of each Derivation Level Structure and the appropriate scribe structure. Also referred to as the Top Level Structure. Naming Convention: The base number appended with \x{201C}MASTER\x{201D}
master cells
Example: DEBF0_MASTER, C5AF0_MASTER

C5AF0_MASTER
C5AF1
C5AF2
C5AF3 C5AF4 C5AF5 C5AF6 -- Derivation Level
C5AF0 -- base level
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master cells
Example: C5AV0_MASTER
Scribe Structure, Derivation Level, C5AV1, C5AV2 C5AV3 No text is needed at the master level when you run LVS; there will be extract errors on global signals that are ok. Example gnd,vdd,agnd,avdd; ALL OTHER EXTRACT ERRORS AT ANY OTHER LEVEL NEEDS TO BE LOOKED AT.
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master cells
Example: C5AV0_MASTER schematic
Derivation Level , C5AV1, C5AV2 C5AV3
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u
DEBU1 DEBU2
master cells
DEBU0_MASTER top level DEBU3 DEBU4 DEBU5 DEBU0 -- base level
Page 2 of 4
DEBU6 -- Derivation Level
This is the hierarchy that should be followed
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extract errors
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LVS training 1;
EXTRACT ERRORS
Incorrect
Correct - Notice the /lvs_ww at the end of the line Once pathname is correct, hit OK
This form will pop up
This is the name of our block: osc_rc8mhz_v3e0_osc_opamp A red circle with a line indicates that LVS failed; there are extract errors and hook-up errors We will take a closer look on the next few pages
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LVS training 1;
EXTRACT ERRORS
Click on Layout Extract Errors to get more information When you have both Layout Extract Errors and block-specific errors, resolve Layout Extract Errors first.
This form appears Our block has 1 texted short and 1 texted open Lets fix them first before proceeding with block checks Click on the text short line
Then on the layout, a line will appear showing you the two nodes that are shorted together (see next page).
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EXTRACT ERRORS
The short is here, between the two Xs. So what can we determine? The line en is shorted to something on the gate of this inverter. On closer look at the inverter, you see text A in metal 1 that should not be there. Remove it on the layout and hit Fixed button.
en
20
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EXTRACT ERRORS
When you correct an error and hit the Fixed button, it will take you to the next error. Because there was only 1 short, it now shows 0 shorts.
Now lets look at the 1 open. Click on the open error. Markers will appear on your layout, identifying the error.
This indicates that the src line is not physically connected everywhere it should be, causing the open. It is connected by text only.
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EXTRACT ERRORS
ERROR FILE (*LAYOUT_ERRORS)
This shows you that there is one short violation
And one open violation
SHORT A node with text Aon it is shorted to a node with text EN on it.
Scroll down in the file to find information about the open. See next page.
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EXTRACT ERRORS
ERROR FILE (*LAYOUT_ERRORS)
Here are details about the open violation
OPEN: In the layout, there is a Text SRC at coordinates 1.2 & 22.7 and at coordinates 25.4 & 53.3
This says there are 2 nodes with the same text label SRC, but are physically unconnected, therefore we have an open.
We make the fix and rerun LVS.
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black_box
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black_box
PAGE 1 of 5
Some thing to know about black_boxes.

If you have layout for the block, the black box only cuts down on your LVS run times. Your final LVS run should not have any black boxes in it if you have layout for the block. An example of this is an aratisanblock
The equivalence file can also contain definitions of BLACK_BOX structures. BLACK_BOX structures are portions of the design that are treated as if they COMPARE, even though no comparison verification has been done on them. Any device and connection data contained within the BLACK_BOX structure is ignored; only the port connections of the black box structures will be checked. A correspondence must be established between the BLACK_BOX ports in the schematic and in the layout using the EQUATE_PORTS construct. For example, the following black box structure is valid: BLACK_BOX schematic = layout {equate_ports { sch_port1=lay_port1 ...sch_portN=lay_portN }}
Flash, vpp pads, use black_boxes
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black_box
BLACK_BOX Syntax
PAGE 1 of 5
BLACK_BOX schematic_name = layout_name {BLACK_BOX Process_Definitions}

The schematic_name option specifies the schematic module name. The layout_name option specifies the layout structure name. The Option_Definitions option indicates optional comparison features within a module. The EQUIV Process_Definitions option regulates processing control for a specific module. For additional information on processing control see the Equivalence File in Hercules LVS User Guide, Chapter 5. The BLACK_BOX Process_Definitions option regulates processing control for a specific BLACK_BOX module. BLACK_BOX Definitions
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black_box
BLACK_BOX Syntax;
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This is a .eqv file used on the YGPP9canc0 chip; see how the block box syntax looks like.
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black_box
LVS Black Box Flow
SCHEMATIC_PERMUTABLE_PORTS = {(c S0 S1 S2 S3 S4 S5 S6 S7)} Figure 45 Decoder (ADR2DEC4) SCHEMATIC_PERMUTABLE_PORTS = { (p (f AIN0 ADR1) (f AIN1 ADR2)) } LVS Black Box Flow To run Hercules LVS COMPARE with black box structures, you must have an ascii text file with a list of black box structures. If you are beginning your Hercules run with a Dracula command file that contains hcell statements, Hercules automatically creates a BLACK_BOX_FILE and specifies the path to the file. If you create a BLACK_BOX_FILE manually, you must specify the path to the file using the HEADER section option, BLACK_BOX_FILE. The syntax for the BLACK_BOX_FILE is as follows:
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PAGE 4 of 5
black_box
LVS = { schematic_structure1 = layout_structure1 ... schematic_structureN = layout_structureN } The BLACK_BOX_FILE contains a list of structures that are treated as if they compare, even though no comparison verification has been completed on them. Any device and connection data contained within the black box structure is ignored. The BLACK_BOX_FILE does not need to contain information about the port connections of the black box structures; Hercules LVS COMPARE determines this information automatically, if the following criteria are met: " The file must specify the name of the both the schematic cell and the layout cell that correspond together. " Every port in the schematic cell must have a corresponding port in the matching layout cell with the exact same port name. However, extra ports may exist in the layout only for cases of PUSH_DOWN_PIN connections, global power/ground connections, and feed throughs.
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black_box
This is a black box .eqv that went out clean
EQUIV sm_nand2_1x=sm_nand2_1x {}
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/* black_box revid=revid {remove_schematic_port = {vddmp, gndmp}remove_layout_port = {vdd, gnd}} EQUIV revid=revid {} */

EQUIV vreg_bg_v1c1_resfb=vreg_bg_v1c1_resfb {} EQUIV eth_10btphy_v1g0_analog10=eth_10btphy_v1g0_analog10 {restrict_merge_series = false, match_by_property=true} black_box artisan_8Kx8_dphd_2005q3v1=artisan_8Kx8_dphd_2005q3v1 {}
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black_box
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This is a chip where a artisan black box was used.

Question, can a TSMC chip streamout just the way the chip Looks on the left side? NO And the reason the answer is no is because it is a bad Practice to do so. The lvs and drc run will be clean As long as the only the port connections of the black
box structures will be checked. Lets just say TSMC outside foundry messes up and does not put the layout in? Then the chip is dead. That is why you must put in the old templet when you stream. TSMC will put In the new updated one when they get it. If you have a big open box like the one in the picture, something is wrong. You need to get the templet from our local TSMC guy or contact the CAD department.
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test-chips
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test-chips
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
What is a test-chip? A test-chip is a in house way that we can test devices on testtestsilicon. The dates they are due out are usually flexible. What is a shuttle? It is usually a outside foundry that has there own processes It is usually a hard core date that has to be met. The foundry sells outside company's spots on a wafer or entire wafers. @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ tarms you need to know: Reticule
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FILL CELLS
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A) for Single product releases, view the chip at the top-level structure. Exp; JE001, DE012
B.) for derivative product releases, Create a new cell and call it Master_Fill. In this cell stack each of the derivative level structures on top of each other at 0,0.
how do you run the fill program?
1.) go to Synopsys Tools button

For Single Products, the Top Level Structure is the Single Product Structure with a placement of the appropriate scribe structures. A Single Product may follow the heirarchy of a Derivation Product if there is a possibility of future derivations. Naming Convention: Mask Number Example: JE001, DE012 For Derivation Products, the Top Level Structure contains a single placement of each Derivation Level Structure and the appropriate scribe structure. Also referred to as the Master Level Structure.
2.) then hit the Run Hercules verification button 3.) then fill out the form-> Run Hercules
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1.) go to Synopsys Tools button

2.) then hit the Run Hercules verification button 3.) then fill out the form-> Run Hercules , make sure the process is right, click the fill button, then hit the ok button
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1.) go to Synopsys Tools button 2.) then hit the Run Hercules verification button 3.) then fill out the form-> Run Hercules , make sure the process is right, click the fill button, then hit the ok button
When you run it you will get this message;
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1.) go to Synopsys Tools button 2.) then hit the Run Hercules verification button 3.) then fill out the form-> Run Hercules , make sure the process is right, click the fill button, then hit the ok button 4.) this will create a .gds file in your issbatch area;
Then you need to stream it in to; How do you stream it in? go to your file button;
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1.) go to Synopsys Tools button 2.) then hit the Run Hercules verification button 3.) then fill out the form-> Run Hercules , make sure the process is right, click the fill button, then hit the ok button 4.) this will create a .gds file in your issbatch area; 5.)Then you need to stream it in to; How do you stream it in? go to your file button; 6.) then to import button 7.) then stream button (the pop up below will show up); put in the location of the fill file that was created, and library name
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1.) go to Synopsys Tools button 2.) then hit the Run Hercules verification button 3.) then fill out the form-> Run Hercules , make sure the process is right, click the fill button, then hit the ok button 4.) this will create a .gds file in your issbatch area; 5.)Then you need to stream it in to; How do you stream it in? go to your file button; 6.) then to import button 7.) then stream button (the pop up below will show up); put in the location of the fill file that was created 8.) hit ok button; this will pop up when it is finished
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1.) go to Synopsys Tools button 2.) then hit the Run Hercules verification button 3.) then fill out the form-> Run Hercules , make sure the process is right, click the fill button, then hit the ok button 4.) this will create a .gds file in your issbatch area; 5.)Then you need to stream it in to; How do you stream it in? go to your file button; 6.) then to import button 7.) then stream button (the pop up below will show up); put in the location of the fill file that was created 8.) hit ok button; this will pop up when it is finished 9.) it creates in your library manager a new library called what ever name you gave it, in this example it was called fill; see below how now it is there;
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10.) now bring up the fill cell for the chip. It is called fill_c5av0
This is what the fill cell may look like below; on this one with no blocking layers used; metal1 metal2 metal3 Are all over the chip
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How do you use the blocking layers? You put blocking layer around the area the engineer wants to protect and does not want the fill over the block. metal fill block layer (blocks all metal layers)
Make sure you run LVS and DRC after you use fill. This is a must!!!!!!! If your engineer knows where a possible fib may take place, it is better to put block layer Around it. You dont need to put block layer around options because it would be a metal rev any way no blocking layer used in two spots blocking layer used close up when blocking layer used
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mask layers
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4. Place the Microchip Logo, Maskright Symbol, and Copyright Symbol from the process appropriate prim Library. (Copy these cells to your local library or flatten them after you place them) Single product release: Place within the product die area in the top-level structure.exp. DEXA1 Derivative product release: Place within the product at the base level structure. Exp. DEBA0
Fracture coods program will verify proper placement of

Microchip Logo, Maskright Symbol, and Copyright Symbol
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Single product release: Place within the product die area in the top-level structure.exp. DEXA1 Derivative product release: Place within the product at the base level structure. Exp. DEBA0
C5AV0 - PLACED IN BASE LEVEL

Base Level A layout structure containing the common hierarchy for all derivative Example: D5AB0
The sd_align_triangle is placed in the base level of the chip over the first letter of the base level name of the chip.
C5AV1 - PLACED IN Derivation Level Structure
Derivation Level Structure:A layout structure containing the Base Level Structure and the options which customize the Base Level Structure Example: D5AB1, D5AB2, D5AB3, etc
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Scribe Structure: A layout structure containing the Mask Name cell and the Mask Revision ID\x{2019}s to be placed in the reticle level scribe streets by Maskmaking.
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Example of a RIN; check the rev against the scribe cell, they must be the same
This is the scribe cell
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Go to the microchip utilities button Then hit scribe test placement button Then hit create scribe cell button Choose the right msl, you get this from the RIN, When you put in the right MSL then hit The apply button, and the layers below it will pop into the box. Then hit ok and it will create the scribe cell, make sure you have a open layout window with nothing in it.
See next page
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make sure you have a open layout window with nothing in it.How do you do this? Hit the file button, then the new, then the cell view button this window will pop up;
This is a new layout window called larry_test, make sure Your in virtuoso and view name is layout here is the new Layout window below with nothing in it. See next page
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Then hit ok, it will build the scribe cell for you
Here is a close up view of the scribe cell
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This program will automatically place the base mask name cell and mask revision ID on the appropriate layers. Place this scribe structure above the product die in the master level structure. Place this cell and the sd_align_triangle within the product die area in the derivation level structure. You may also place additional critical mask revision ID within the product die area in the derivation level structure as per engineering request.
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RIN
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Example of a RIN
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Example of a RIN PAGE 1
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Example of a RIN PAGE 2; LAYOUT make sure extent limits coords are on RIN
Verify that all mask revision levels match the RIN The mask revision levels are in the scribe cell
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extent box coordinates

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The extent box coordinates are from the bottom left corner of the chip, in most cases (0,0) to the upper right corner of the chip.
The EXT BOX defines the edge of the die and die scribe ring location the scribe ring goes on the edge of the EXT BOX, the outside of the scribe ring is where they saw the die. where the EXT BOX is located in relationship to the chip depends on the process. to find the extent box coordinates fast do the steps below; 1.) Microchip Utilities hit the button 2.) go to coordinates Utilities 3.) then hit extent box coordinates
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to find the extent box coordinates fast do the steps below;
1.) Microchip Utilities hit the button 2.) go to coordinates Utilities 3.) then hit extent box coordinates this box will pop up
So the size of this chip was: (0,0) by (7694.2,7798.6)
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how to run list cells

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u to microchip utilities button 1.) go

2.) then hit the streamout checklist button 3.) then hit list cells a pop up will appear; 4.) then fill out the form, this will create a file in your working directory, its location will be like example:
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Below is a example of an listcells output file, all the errors below need to be fixed. What the error is saying is that there is a reference cell from a reference library in the local data base. So you have the locked down copy of the cell in your reference library, but you have a copy of the same cell, with the same name in your data base that can be edited. This is not allowed! You most remove the cell from your local library and have it point to the locked cell in the reference library. (a reference library also called beta; a reference library and beta are the same thing) /home/data_az/ltrain/virt/listcells.C5AV0.lay
List cells results,
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when you do the finial listcells, you need to use the tape out version.
It will put the finial results in a location like the path below:
/home/data_az/ltrain/virt/listcells.C5AV0.lay LAYOUT
unused cells program
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unused cells program

u
1.) go to microchip utilities button 2.) then hit the streamout checklist button 3.) then hit unused cells a pop up will appear; 4.) this pop up will show up when it is finished running
On the right side is what the results will look like; What this is saying the cells on the list are not in The chip at the level I ran it. This must be ran at the Top level of your chip, or the master level if you have one.
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hidden cells program

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u
1.) go to microchip utilities button 2.) then hit the streamout checklist button
hidden cells
3.) then hit hidden cells a pop up will appear; 4.) this pop up will show up when it is finished running
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how to use name checker

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So how do you run name_checker?

You must be in your issbatch lvs verification directory Example;
Then run name_checker.pl

It will put the results in a directory called compare.out
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Viewing the results of name_checker.pl
Names like this Should be fixed in The layout
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explode and flatten program

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Go to the microchip utilities button, Then hit Streamout checklist button Then hit explode and flatten button, then a pop up will appear like the one below; MSG: Output log will be written to a area like one below /home/data_az/DECR0cana1/virt/explode.out Note this program will be exploding paths
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.cds.lib
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step by step through the stream out check list
u #13D; LINE
below is a .cds.lib example
_____ Clean up the cds.lib file. What this is saying you should clean up is, pointers pointing to things like obsolete. What you want pointers to is your, local, td, beta (reference libraries)! Only have one main library , you do not want to have pointers pointing to other library's.
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restrict_merge_series=false
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This is one of the hardest LVS errors to find and know how to deal with. This error happens a lot in analog layouts; when you run the block this is what the error looks like in digital layouts. When you Try to follow the error by tracing the nets all will be fine. The problem is the LVS tool has trouble with the odd sized devices in the layout. See schematic on next page.
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Notice the schematic, the devices are a strange size, this causes the LVS tool to get lost. The way to Fix this is go to the .eqv file and put at the cell level restrict_merge_series=false, see next page
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In analog, the layout devices that causes the LVS tool to get lost are, two gates on the same peace of diffusion, in series and you want to collapse them. The way to Fix this is go to the .eqv file and put at the cell level restrict_merge_series=false, see next page
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In analog, the layout devices that causes the LVS tool to get lost are, two gates on the same peace of diffusion, in series and you want to collapse them. The way to Fix this is go to the .eqv file and put at the cell level restrict_merge_series=false, see next page
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restrict_merge_series=false to fix this is go to the .eqv file and put at the cell level
Error happens
Fixed error
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This is a clean output after the, restrict_merge_series=false is put in
the .eqv file
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enlarging a flat contact or via in mass

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You need to grab all in this case via3, view only the via3 and grab them; STEP:1
STEP:2 Go to create box:
Then go to layer generation button (next page) LAYOUT

STEP3: Then go to layer generation button (this menu will pop up); I am growing The via3 by .05 in every direction (hit apply) STEP:3
STEP:4
Then go to the edit button and go down to merge button and merge, The reason you need to do this is because the layer generation button Put the new bigger via on top of the old smaller one, so you need to LAYOUT merge them together.

STEP5: You need to grab all in this case via3, view only the via3 and grab them; Then hit merge (this will merge the old smallvia3 with the new large via3: STEP:5
notice the white box is the old is via3 now after merge it is gone and only the larger via3 is now there;
old small via3 large via3 on top of old one
STEP:6
new large via3 merged
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how to substantiate a cell into your library

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u how to substantiate a cell into your library

In this case we are taking a cell from the tsmc18rf model, what this is, is the standard cells from tsmc for .18 technology. The reason we are Doing this is because in running LVS we had a resister that we could not Match. The reason is the device is most likely built wrong, so we are going to tsmc18rf modelwhere they have one built with all the right layers on it, then we can compare it to the one in our layout and see the differences and fix the one in the layout; so we went to the cadweb under layout then to primitive libraries then pick the one you need in this case tsmc18rf model, a list of all the cells are there;
STEP 1;
This is the cell We need to bring into our layout Library. LAYOUT

So what is this telling us? This is the library name the cell is in
This is the cell name in the Schematic This is the model Name in Tsmc18rf library For that 3: STEP cell LAYOUT

Next make sure the library shows up in the design manager list of libraries; as you see below it is there; (tsmc18rf ) Next hit lower case i a menu pops up create instance
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This is the library the cell is coming from This is the cell name in that library (note; it is a different name then the Device in the schematic, you must Change the name if you want to Run LVS on it; Based on the schematic you put in the (w) width And the (l) length
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This is how to read the schematic; the width 0.58 put in here; length here;
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Then you place the cell in this case a resister in your block; just click in your layout window and it is there;
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quick checks for IDC chips

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u FIRST THING TO DO IN CHANDLER LAYOUT
IDC chips
Chandler layout
Send a preliminary stream out to CATS to check to data and rev layers. This can save us up to a day. Have cats check only rev layers. This will help streamline the process at the final hour.
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India Streamout Procedure for Chandler layout

We encourage IDC to send an almost final gds over to cats for them to do a preliminary check to validate the data. This will help streamline the process at the final hour. (added 1/6/06)
Receive the Stream out Check list, be sure that there are signed waivers for any and all lvs, drc or antenna errors attached and that the Stream out check list has been completed. Check item #15 on the Stream out Check list - Verify that there are no opens, shorts or illegally drawn devices in the .LAYOUT_ERRORS file. Check over the memory cell orientation output file to verify that all memory cells are oriented correctly. Check the preliminary PCF file against the final PCF file to verify there are no differences between them for stream out (A0 revisions only). Verify the layout_doc area has all the necessary documentation in it for future revisions of the product. Review the xor output to verify that only the layers of interest were changed (A1 and up revisions only). Initial the SP box on items 9, 10 & 15 on the Stream out Check list. Check the gdsII directory in the project to verify there is a final .gds file created by IDC. Contact John Simpson in CATS when ready to stream out. Email appropriate India & Chandler contacts when the streamout is complete.
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step by step through the stream out check list Page 1 of 57 u (quick check for IDC chips)
Form FRM-47007-1 This is what the Stream out checklist looks like. When you get a Chip from IDC, This should be filled out by the layout designer in IDC, and the design project leader, you just need to check off 3 things in Chandler LAYOUT
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(quick check for IDC chips)
Chandler needs to check off lines; 9 10 15 PCF: Pad Coordinate File documents each pad opening coordinate. This file is used to order Probe Cards and for packaging. LAYOUT
u # 9; LINE
Page 3 of 57
(quick check for IDC chips) STEP: 1
9. ______(LD)______(DE)______(SP) Create the final PCF file: Use the \x{201C}Create Pad Coordinates File \x{2026}\x{201D} program to generate a final pad coordinate file (PCF-mask#) for each new product. Attach the PCF to a general purpose CN FRM-00008 with signatures from the lead design engineer, lead layout designer, and mask making. Deliver the hard copy with signatures and an electronic copy of the PCF to Document Control (email to DMS Chandler). Create a PCF file for a product revision only if the rev A0 PCF does not exist in document control _____ Assembly engineering has approved the preliminary product bondout for all applicable packages. _____ The final PCF must match the Assembly approved preliminary PCF. (Bond pads cannot move after Assembly\x{2019}s approval).
If this is a rev. exp; a1,b0 you have to do nothing, just put a N/A on line #9
What does a pcf file look like? (see next page) PCF: Pad Coordinate File documents each pad opening coordinate. This file is used to order Probe Cards and for packaging. LAYOUT
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Page 4 of 57
STEP: 1 only need to do if the rev A0 PCF does not exist in document control
9. ______(LD)______(DE)______(SP) Create the final PCF file: Use the \x{201C}Create Pad Coordinates File \x{2026}\x{201D} program to generate a final pad coordinate file (PCF-mask#) for each new product. Attach the PCF to a general purpose CN FRM-00008 with
signatures from the lead design engineer, lead layout designer, and mask making. Deliver the hard copy with signatures and an electronic copy of the PCF to Document Control (email to DMS Chandler).
What does a pcf file look like, and how do you get it? 1.) go to chipnews on the internet; 2.) go to Document Management; 3.) go to DSM-FORMS; 4.) then hit the search button and put in the number of the form (in this case FRM-00008) 5.) then hit the attachment word button; (this will but the form where you want it placed) in this case in the project directory; 6.) fill out the form electronic copy on line, then print it out for a hardLAYOUT copy for sign offs; (see next page)
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step by step through the stream out check list Page 6 of 57 u # 9; (quick check for IDC chips) LINE STEP: 1
When IDC sends us information it comes in a email like this one;
Each line here states; 4450_RevA2_DRC.PDF (This is the drcs they waved) There copy of the stream Out check list with initials The fracture_coordinates.pdf
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When IDC sends us information it comes in a email like this one;
Each line here states; 4450_RevA2_DRC.PDF (This is the drcs they waved) There copy of the stream Out check list with initials The fracture_coordinates.pdf
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u # 9; LINE
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4450_RevA2_DRC.PDF (This is the drcs they waved)
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u # 9; LINE
Page 8 of 57

There copy of the stream Out check list with initials
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The fracture_coordinates.pdf
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step by step through the stream out check list Page 10 of 57 u # 9; (quick check for IDC chips) LINE STEP: 1 If this is a rev, or a electronic copy of the PCF was sent to Document
Control, the stream out check list will look like this; in this case put an n/a, not necessary in the blank line; notice also the two below
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step by step through the stream out check list Page 11 of 57 u # 9; (quick check for IDC chips) LINE STEP: 1 If this is a rev, A0
9. ______(LD)______(DE)______(SP) Create the final PCF file: Use the \x{201C}Create Pad Coordinates File \x{2026}\x{201D} program to generate a final pad coordinate file (PCF-mask#) for each new product. Create a PCF file for a product revision only if the rev A0 PCF does not exist in document control
How to Create Pad Coordinates File

TO SEE how_to_create_pcf_file in this reference manual 1.) GO TO THE COORDINATES UTILITLES BUTTON (hit it a drag down will pop up) 2.) GO TO PAD CORRDINATES (dump pads cadence only)
(hit it a pop up will show up called Dump Pads Form)
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Create a PCF file for a product revision only if the rev A0 PCF does not exist in document control The first one you send is the preliminary and must be oked by Assembly engineering; IDC must send us the preliminary one that has been approved! If they have not done one you need to send a preliminary and must be oked by Assembly engineering before you send a final coords;
When you run this it will put the results in your project virt Directory; Be careful here, do not jump the gun; we have been bet on sending a final Before the preliminary was ok; one case the pad was on the wrong side of the chip and the chip went out to the fab. IT MUST GET AN OK ON THE LAYOUT PRELIMINARY, BEFORE YOU SEND THE FINAL TO ASSEMBLY
When you get the preliminary back and oked; check and make sure the pads have not moved; compare the coordinates, they need to be the same; _____ The final PCF must match the Assembly approved preliminary PCF. (Bond pads cannot move after Assembly\x{2019}s approval).
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step by step through the stream out check list Page 14 of 57 u #10; (quick check for IDC chips) LINE STEP:2
10. ______(LD)______(DE)______(SP) Verify that the base memory cells and base fuse cells are oriented the same using \x{201C}Check Cell Orientation \x{2026}\x{201D}. Enter the name of all base memory cells. Fix any errors. _____ 160k Products: Check the base memory cell separately from base fuse cell.
You are checking the orientation of the memory cells against the memory cells; You are checking the orientation of the fuse cells against the fuse cells;
The memory does not have to be in the same orientation as the fuse cells;
What is a base memory cell you run? Push into the memory cell layout until you get to the bottom cell What is a base fuse cell you run? Push into the fuse cell layout until you get to the bottom cell LAYOUT
step by step through the stream out check list Page 15 of 57 u #10; Verify that the LINE
base memory cells and base fuse cells are oriented the same; YOU ARE CHECKING FUSE VS MEMORY CELL; THE EXCEPTIONS ARE 160K, Check Cell Orientation program;
1.) Microchip Utilities hit the button 2.) Cell Utilities 3.) Cell Orientation coordinates this box will pop up
WHAT ARE THE NAMES IN PUT IN HERE? Exps; NAME; td160_xcell_a: this is the memory cell td160_ziner_a : this is a fuse cell td160_Peecredfuse_a :this is a fuse cell you will need to check where your pointers are pointing too, by looking at your reference libraries; LAYOUT See next page
step by step through the stream out check list Page 16 of 57 u #10; Verify that the FUSE VS MEMORY CELL LINE
base memory cells and base fuse cells are oriented the same; YOU ARE CHECKING FUSE VS MEMORY CELL; THE EXCEPTIONS ARE 160K, Check Cell Orientation program;
1.) Microchip Utilities hit the button 2.) Cell Utilities 3.) Cell Orientation coordinates this box will pop up, there is a space between names
WHAT ARE THE NAMES IN PUT IN HERE? Exps; NAME; td160_xcell_a: this is the memory cell td160_ziner_a : this is a fuse cell td160_peecredfuse_a :this is a fuse cell We are checking the orientation of the memory cell against the orientation of the LAYOUT fuse cell See next page
step by step through the stream out check list Page 17 of 57 u #10; Verify that the FUSE VS MEMORY CELL LINE
base memory cells and base fuse cells are oriented the same; YOU ARE CHECKING FUSE VS MEMORY CELL; THE EXCEPTIONS ARE 160K,
Here was the results, this tells us the fuse and memory are not at the same orientation, therefore it is a error
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Verify that the base memory cells and base fuse cells are oriented the same Check Cell Orientation program
Check Cell Orientation program;

1.) Microchip Utilities hit the button 2.) Cell Utilities 3.) Cell Orientation coordinates this box will pop up
WHAT ARE THE NAMES IN PUT IN HERE? Exps; NAME; td160_xcell_a: this is the memory cell td160_ziner_a : this is a fuse cell td160_Peecredfuse_a :this is a fuse cell you will need to check where your pointers are pointing too, by looking at your reference libraries; LAYOUT See next page
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(quick check for IDC chips) STEP:2
you will need to check where your pointers are pointing too, by looking at your reference libraries; To do this go to your tools bar and a pop up will pop up; Then hit library path editor; Another pop up will come up like the one below; So where does this tell us to look for the memory and fuse cells?
The pointers are pointing to this library

So what are the steps to Tell what my lower level Memory cell name is and My fuse name is?
See next page
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Check the base memory cell separately from base fuse cell or cells. 1.) run list cells 2.) push into the layout till you reach the lower level; write the names down 3.) then run, Check Cell Orientation program; make sure you run this from the top of the chip level, save your output:
see next page:
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Page 21 of 57
Check the base memory cell separately from base fuse cell or cells. This must be ran at the top level; program Check Cell Orientation program
Lowest level memory cell--- td160_xcell_a
See the results that poped up on the next page;
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Page 22 of 57
STEP:2
Notice it was ran at the top level
So what is this telling us? This tells us that there is an error in the memory cell That must be fixed, there is a cell in the memory with the wrong orientation; let us go look at the layout and see what the problem is; see next page
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Page 23 of 57
STEP:2
So lets look at the problem in the layout: notice at the far left the poly 1 is at a different orientation then the rest of the poly 1; this is an error
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Page 24 of 57
STEP:2
This is what a clean run looks like when you ran Check Cell Orientation program
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Verify that the base memory cells and base fuse cells are oriented the same Check Cell Orientation program
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15. ______(LD)______(DE)______(SP) Review final verification: Antenna: The antenna <product name>.LAYOUT_ERRORS file should be empty. _____ Waivers completed. (Use the <product name>.LAYOUT_ERRORS file as waiver) DRC: Any remaining errors must be fixed or waived by the appropriate engineering group. _____ Waivers completed. (Run \x{201C}error_read\x{201D} on <product name>.LAYOUT_ERRORS to create waiver) LVS: Run with (lvs_ww) and without wells (lvs_wow) for each product. A clean lvs includes: _____ <product name>. LAYOUT_ERRORS file is empty or errors are explained. _____ Run \x{201C}Compare Pins (single cell)\x{201D} on your top-level structure. Check output file to verify that layout pin names match schematic pin names. _____ No \x{201C}Texted Opens\x{201D} are allowed except for power and ground with engineering approval. _____ Fix all property warnings. _____ Waivers completed. (Use the <product name>.LVS_ERRORS file as the waiver) _____ Check that black boxes are in place when using external IP that cannot be verified.
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u #15; LINE
what_is_an_antenna?
The Antenna check is designed to flag any metal1 lines that have greater than a 50 to 1 ratio. ie. a long metal1 line tied to a small gate. The reason this check is in place is because after metal1 deposition, there is a plasma etch operation. During this etch there is a charge gain on the metal1 lines. If the metal1 to gate ratio is greater than 50, you can potentially blow the gate oxide. causing the gate to fail.
To fix this type of violation you may, in order of preference,

1) Break your metal1 close to the gate by jumpering the line to metal2. Jumpering in poly2 does nothing. (see cad before going to step two) 2) Place a low voltage nactive surrounded by pwell diode anywhere on the metal1 line.
If you place a high voltage diode on the line, you will actually create a worse violation than that antenna problem. Any well that has a device that can potentially go to high voltage is considered a high voltage well.
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u #15; LINE
Page 28 of 57
(quick check for IDC chips) STEP:3a
15. ______(LD)______(DE)______(SP) Review final verification: Antenna: The antenna <product name>.LAYOUT_ERRORS file should be empty. _____ Waivers completed. (Use the <product name>.LAYOUT_ERRORS file as waiver) What is an antenna check? A specialized DRC check which informs the user of long metal lines tied to small poly2 gates. So how do you run antenna? 1.) go to system tools button (pop up will show up 2.) hit run hercules verification button (this form will pop up) click this button
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u #15; LINE
Page 29 of 57
15. ______(LD)______(DE)______(SP) Review final verification: Antenna: The antenna <product name>.LAYOUT_ERRORS file should be empty. _____ Waivers completed. (Use the <product name>.LAYOUT_ERRORS file as waiver) So how do you run antenna? 1.) go to system tools button (pop up will show up 2.) hit run hercules verification button (this form will pop up) 3.) then hit ok button; this submits the job. When the job is finished it will look like this below in your
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u #15; LINE
Page 30 of 57
15. ______(LD)______(DE)______(SP) Review final verification: Antenna: The antenna <product name>.LAYOUT_ERRORS file should be empty. _____ Waivers completed. (Use the <product name>.LAYOUT_ERRORS file as waiver)
the results will be placed in a file under your project directory; see example below;
1.)Your project directory 2.)your rev directory 3.)go into antenna directory Do a more on your
<product name>.LAYOUT_ERRORS
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u #15; LINE
Page 31 of 57
15. ______(LD)______(DE)______(SP) Review final verification: Antenna: The antenna <product name>.LAYOUT_ERRORS file should be empty. _____ Waivers completed. (Use the <product name>.LAYOUT_ERRORS file as waiver) So how do you run antenna? 1.) go to system tools button (pop up will show up 2.) hit run hercules verification button (this form will pop up) 3.) then hit ok button; this submits the job. 4.) to view your antenna job and check it; a.) the results will be placed in a file under your project directory; see example below;
This is what a clean run looks like
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u #15; LINE
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15. ______(LD)______(DE)______(SP) Review final verification: Antenna: The antenna <product name>.LAYOUT_ERRORS file should be empty. _____ Waivers completed. (Use the <product name>.LAYOUT_ERRORS file as waiver) This is what a dirty one looks like, one error found, at coordinates
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u #15; LINE
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15. ______(LD)______(DE)______(SP) Review final verification: Antenna: The antenna <product name>.LAYOUT_ERRORS file should be empty. _____ Waivers completed. (Use the <product name>.LAYOUT_ERRORS file as waiver)
How do you fix antennas?

1) Break your metal1 close to the gate by jumpering the line to metal2. Jumpering in poly2 does nothing. (see cad before going to step two) 2) Place a low voltage nactive surrounded by pwell diode anywhere on the metal1 line.
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u #15; LINE
1)
Page 34 of 57

Break your metal1 close to the gate by jumpering the line to metal2. Jumpering in poly2 does nothing. (see cad before going to step two) During this etch there is a charge gain on the metal1 lines. If the metal1 to gate ratio is greater than 50, you can potentially blow the gate oxide. causing the gate to fail. So if you add the pgate and ngate together the ratio of the metal line can not be greater then 50. The safest way to do an antenna is like below;
Metal 1 Metal 2 via
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u #15; LINE
Page 35 of 57

2) Place a low voltage nactive surrounded by pwell diode anywhere on the metal1 line. This way to fix it is more dangeris then the first way, Make sure you are using low voltage pwell, if you use high voltage pwell you will fry the part. Below is the right way using low voltage
Low voltage pwell Nact It makes a diode
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u #15; LINE
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(quick check for IDC chips) STEP:3b
15. ______(LD)______(DE)______(SP) Review final verification: DRC: Any remaining errors must be fixed or waived by the appropriate engineering group. _____ Waivers completed. (Run \x{201C}error_read\x{201D} on <product name>.LAYOUT_ERRORS to create waiver) Design Rule Check (DRC): Verification procedure to ensure all physical patterns with in a structure adhere to the specified DR spec
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u # 15; LINE
Page 37 of 57
(quick check for IDC chips) STEP:3b
15. ______(LD)______(DE)______(SP) Review final verification: DRC: Any remaining errors must be fixed or waived by the appropriate engineering group. _____ Waivers completed. (Run \x{201C}error_read\x{201D} on <product name>.LAYOUT_ERRORS to create waiver)
(This is the drcs they waved)
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u # 15; LINE
Page 38 of 57
(quick check for IDC chips) STEP:3c
15. ______(LD)______(DE)______(SP) Review final verification: LVS: Run with (lvs_ww) and without wells (lvs_wow) for each product. A clean lvs includes: _____ <product name>. LAYOUT_ERRORS file is empty or errors are explained. _____ Run \x{201C}Compare Pins (single cell)\x{201D} on your derivation structures. Check output file to verify that layout pin names match schematic pin names. _____ No \x{201C}Texted Opens\x{201D} are allowed except for power and ground with engineering approval. _____ Fix all property warnings. _____ Waivers completed. (Use the <product name>.LVS_ERRORS file as the waiver) _____ Check that black boxes are in place when using external IP that cannot be verified.
(quick check for IDC chips) 1.) look in the project directory; in this case this was the path,
/home/data_az/DECR0cana1/layout_doc/DECR0cana0/verification/DECR0_MASTER/lvs_ww A.) look at file <product name>. LAYOUT_ERRORS
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u # 15; LINE
Page 39 of 57
(quick check for IDC chips) STEP:3c so if you

this part was run at the Master level, that means that there Master Level Structure: A layout structure containing a single placement of each Derivation Level Structure and the appropriate scribe structure. Also referred to as the Top Level Structure. In This case there where 6 Derivation Level Structures Placed in master, so the 6 Opens seem to be between Derivations See next page
got this result back after running lvs at the master level, would you say this is clean, or would you rerun it and see where the opens are at?
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u # 15; LINE
Page 40 of 57
(quick check for IDC chips) STEP:3c

The red box here that is highlighted should be something that gets a close look at, The reason why is the job was ran at the master level and the errors here are at a lower level. This should always be checked to make sure it is not a real error. In this case it is a false error because of the zener cell. See next page
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u #15 LINE
STEP:3c When I ran lvs_ww on the master level, this was what I got back;
Notice that there are 5 opens at the master level When I went to them they all were between Derivations, that is ok at the master level. The Color lines above represent the 5 opens.
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u #15 STEP:3c (quick check for IDC chips) LINE
Page 42 of 57
so now I know what the opens are at the top level and they are ok. What about the extract errors at the base level, (Nwell not tied to vdd/vddio/avdd/avddio) The engineer waved them and said they are ok, so now lets look at the extract errors in the zener cell; in this case the engineer waved them also; so now I can sign off on this
LVS:Run with (lvs_ww) and without wells (lvs_wow) for each product.A clean lvs includes: _____ <product name>. LAYOUT_ERRORS file is empty or errors are explained.
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u # 15; LINE
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(quick check for IDC chips) STEP:3d
15. ______(LD)______(DE)______(SP) Review final verification: _____ Run \x{201C}Compare Pins (single cell)\x{201D} on your derivation structures. Check output file to verify that layout pin names match schematic pin names.
1.) so how do you run Compare Pins ? A.) go to microchip utilities B.) go to pin/label utilities C.) go to compare pins (single cell)a pop up will show up, this is not where the schematics is located so it needs to change to be like the second window
LAYOUT
(quick check for IDC chips) This is what the results looked liked when I ran it;
Page 44 of 57
Is this clean? NO, notice it is case sensitive on pad names; this chip did stream But the names should have been changed to lower case: Yes, the chip did work
LAYOUT
(quick check for IDC chips) This is what the results looked liked when I ran it;
Page 45 of 57
Is this clean?
LAYOUT
Page 46 of 57
(quick check for IDC chips) STEP:3e
15. ______(LD)______(DE)______(SP) Review final verification: Check output file to verify that layout pin names match schematic pin names. _____ No \x{201C}Texted Opens\x{201D} are allowed except for power and ground with engineering approval. (we do allow texted opens at the master level, but none at the derivation level)
This was a lvs run at the master level note that there were 5 opens; when
We checked the opens, the opens were between the derivations that wasLAYOUT ok;
Page 47 of 57
LAYOUT
Page 48 of 57
LAYOUT
Page 49 of 57
(quick check for IDC chips) STEP:3f
15. ______(LD)______(DE)______(SP) Review final verification: _____ Fix all property warnings.
Notice the yellow warning signs, when we click on them it shows us

property warnings that must get fixed before you stream out!
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Page 50 of 57
(quick check for IDC chips) STEP:3f
15. ______(LD)______(DE)______(SP) Review final verification: _____ Fix all property warnings.
Another way to see if you have property warnings is to look at the equivalence summary file(sum..) under VIEW; see example below; all devices & nets are matched but device property warnings are here:
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Page 51 of 57
(quick check for IDC chips) STEP:3g
15. ______(LD)______(DE)______(SP) Review final verification: _____ Waivers completed. (Use the <product name>.LVS_ERRORS file as the waiver)
LAYOUT
u STEP:3g
Page 52 of 57
15. ______(LD)______(DE)______(SP) Review final verification: _____ Waivers completed. (Use the <product name>.LVS_ERRORS file as the waiver) This is an example of where you will find the <product name>.LVS_ERRORS file as the waiver
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u STEP:3g
Page 53 of 57
15. ______(LD)______(DE)______(SP) Review final verification: _____ Waivers completed. (Use the <product name>.LVS_ERRORS file as the waiver) This is an example of what you will have the engineer sign <product name>.LVS_ERRORS file as the waiver Notice the opens are all at the DECH0_MASTER level and are all pads; the 31 violations found as opens were all between derivation level
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u STEP:3g
Page 54 of 57
15. ______(LD)______(DE)______(SP) Review final verification: _____ Waivers completed. (Use the <product name>.LVS_ERRORS file as the waiver) This is an example of what you will have the engineer sign <product name>.LVS_ERRORS file as the waiver, anything in here you must have the engineer look at to be safe;
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u STEP:3h
Page 55 of 57
15. ______(LD)______(DE)______(SP) Review final verification: _____ Check that black boxes are in place when using external IP that cannot be verified.
BLACK_BOX Definitions
This chip has a block box in it.
LAYOUT
u STEP:3h
Page 56 of 57
15. ______(LD)______(DE)______(SP) Review final verification: _____ Check that black boxes are in place when using external IP that cannot be verified.
BLACK_BOX Definitions
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Page 57 of 57
CHANDLER LAYOUT
IF YOU CHANGE ANY THING IN THE CHIP, exp; REV LAYERS MAKE A EDIT, CHANGE THE FILL. YOU MUST DO; 1.) RSYNC TO (IDC) SO THEY HAVE THE SAME DATA AS WE HAVE. TO DO THIS SEE SYSTEM MEM. GROUP. AFTER THIS IS DONE THEN HAVE SYSTEM MEM SHOUT DOWN THE RSYNC.
LAYOUT
How to open a zip file u
Page 1 of 5
This is an example of a email with an attachment that is in a zip file example; PIC18F4520B1.zip
LAYOUT

zip file example;
Page 2 of 5
PIC18F4520B1.zip
How do you open this; click on the name of the zip file twice; (a pop up will appear)
Then hit ok twice; (a pop up will appear) see next page
LAYOUT

zip file example;
click on the name of the zip file twice; (a pop up will appear)
Page 3 of 5
PIC18F4520B1.zip
This is all the files that where in the zip file; LAYOUT

zip file example;
Then hit open; (a pop up will appear)
Page 4 of 5
PIC18F4520B1.zip
Then hit ok, it will put it in your home area
LAYOUT

zip file example;
PIC18F4520B1; cd into PIC18F4520B1;
Page 5 of 5
PIC18F4520B1.zip
Then cd into the file that was created in your home area; in this case it is called,
These are the files that need to be printed; This command prints the file; enscript -2r DECH0_B1_RIN.pdf
LAYOUT
How to print a .pdf file

enscript -2r DECH0_DRC.pdf Command, two rows, file name
LAYOUT
flatten files
Example of a flatten file;
flatten = eth_10btphy_v1g0_analog10 explode_all = vreg_bg_v1c1_pwaf_row_pair,vreg_bg_v1c1_pchout,eth_10btphy_v1f0_R1600
Use vi to create a flatten file; When do you use commands? flatten flatten stays at the level, does not inherit children explode moves up 1 level and that level you move up to inherits children explode_all flattens then explodes delete deletes cell it will not check any structures beneath it (all goes away) To create a new flatten file; this will open a new file were you can type in your commands Type vi flatten
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technology file issues

LAYOUT
what do you do if you have technology file u issues?

Some examples below: notice no layer colors are defines;
Page 1 of 3
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Page 2 of 3
so what do you do next? I went to my virt area and looked for what technology files I had there. See below; this is the one I need to point to
So how do I point to it? Go to your LSW window and hit edit a pop up will show up, then hit the display resource editor button and another window will pop up; it will look like the one below; then hit the file button, then the load button, another pop up will pop up like the one below;
LAYOUT
Page 3 of 3
so what do you do next? We want to load the technology file from my home area; you can point to someone else's technology file by pointing to it by putting the path to it in here. I added the path to My virt area so I can use my tech file with my colors. Then hit ok, it will load it:
LAYOUT
shortest path
to find shorts
LAYOUT
Shorts will be under your extract errors; hit extract errors to see them; then go to the Options button and hit shortest path this pop up will show up; then hit the text (short) Line and it will fill out the form for you; see next page
how to run shortest path to find shorts 1 of 2 Page u
LAYOUT
then hit the text (short) Line and it will fill out the form for you; then hit the generate button and it will run shortest path for you; notices it is flagged in the layout
how to run shortest path to find shorts 2 of 2 Page u
LAYOUT
macro structure format

LAYOUT
macro structure format, layout designers and have them always follow this format when they work on analog modules? It would be very helpful if they place their layout documents following the format outlined in this chart so we do not have to re-structure them when we are checking the macros into iplib. Often times the layout file permissions are locked and it requires extra effort to go back to these layout
project when the layout designers have already move on to another project. It would make the iplib check in process more efficient.
macro structure format
LAYOUT
issnetlist
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making a netlist
B
2 of 4
You must run: avanti_netlist [--spice] <Technology> [library ...] command_file A single technology must be specified. Valid options are: --tsmc, --ams, --200k, --185k, --160k, -140k, --130k, --tsmc_018
avanti_netlist --160k bytex2.cmd
Must have the -LAYOUT
2 of 4
how to create two files that LVS Common mistakes: needs

avanti_netlist bytex2.cmd No --160k given avanti_netlist 160k bytex2.cmd Missing --160k before 160k This is the right way: avanti_netlist --160k bytex2.cmd This will produce the files below: bytex2.iss bytex2.eqv These are the two files you will need to run LVS jobs LAYOUT
2 of 4
LVS components
This tells you that your avanti_netlist worked
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netlist
This is the home project area BEFORE creating an HSPICE NETLIST; notice there are no osc_rc8mhz_v3e0_osc_opamp files.
LAYOUT
STEP 1 CREATE AN HSPICE NETLIST

A.) Open the schematic file for your layout B.) Click on Microchip pull-down menu C.) Select HSPICE netlisting This form will pop up:
LAYOUT

Fill out HSPICE Netlisting Options form:
Select Show log file Select your process technology Select LVS netlist Hit OK to create netlist
This will create a netlist file in this directory named: osc_rc8mhz_v3e0_osc_
opamp.hspice (your block name with .hspice extension)
LAYOUT
After creating your .hspice netlist, list (ls) your project directory. Notice a new file called osc_rc8mhz_v3e0_osc_opamp.hspice.
LAYOUT
STEP 2 CREATE A .CMD FILE

Create a command file ( .cmd file) by typing in the following line: echo <your_block_name.hspice> > <your_block_name.cmd> ex. echo osc_rc8mhz_v3e0_osc_opamp.hspice > osc_rc8mhz_v3e0_osc_opamp.cmd
Note: the command file contains only one line: the hspice file name
LAYOUT
STEP 3 RUN AVANTI_NETLIST

Run avanti_netlist on the .cmd file to create the files needed to run LVS
ex. avanti_netlist --tsmc_025emf sn osc_rc8mhz_v3e0_osc_opamp.cmd --tsmc_025emf Process standard cell library block you are running ,cmd (command file)
LAYOUT

After running avanti_netlist, run more on your nettran.log file (this will tell you if avanti_netlist ran successfully)
avanti_netlist --tsmc_025emf osc_rc8mhz_v3e0_osc_opamp.cmd (incorrect way) vanti_netlist --tsmc_025emf more nettran.log If it was not successful (in this case, avanti_netlist command was missing the library sn), you will get this error message:
avanti_netlist --tsmc_025emf sn osc_rc8mhz_v3e0_osc_opamp.cmd --tsmc_025emf
(correct way)
If it was successful, you will get this message:
LAYOUT

Avanti_netlist creates two new files needed to run LVS: .eqv file .iss file Type ls to confirm that the new files appear in your project directory. Save the .eqv file to .eqv.gold the first time, so it will not get overwritten.
14
LAYOUT
STEP 4 SUBMITTING YOUR LVS RUN

1.) In layout, click on Synopsys Tools pull-down menu 2.) Select Run Hercules Verification 3.) Fill out the Run Verification form
Make sure to enter the correct process technology Select lvs_ww (lvs with wells) Enter the.iss and .eqv file names in the lines below. You will need the complete path to your project directory. Schematic Netlist (.iss) file
(your_block_name.iss)
Schematic Equiv (.eqv) file

(your_block_name.eqv)
You may also need to use an explode / flatten file, eg. if using PMOS structures in an N-well, where the well is on a different level of hierarchy than the PMOS. The file would have a .flatten extension. Hit OK to submit LVS run to the queue. This can take a few minutes, depending on the size of your layout.
LAYOUT
STEP 4 FORM FILLED OUT WRONG
Note: This lvs run will not work because of the blank space in the schematic equivalency file line
16
LAYOUT
STEP 5 CHECK YOUR RESULTS

If the netlist files were generated properly and exist in the right location, you will see: Job Submitted successfully in your CIW. You can type qq in your terminal window to see the status of your LVS run.
When LVS run is done, you will see: Job completed, check your results To view your results, click on Synopsys Tools button, then select Start Explorer LVS
This form will appear In the Hercules run directory, you must enter the type of job being run; if you ran LVS_WW, you must add /lvs_ww to the end of the line If you hit OK or Apply without adding the additional directory to the path, RESULTS WILL BE INVALID
LAYOUT
EXAMPLE OF GOOD USAGE OF GUARD-RINGS GUARDon an ESD PAD

This layout was used on a chip that worked
LAYOUT
ESD PAD EXAMPLE OF BAD USAGE OF GUARD-RINGS GUARDESDlatchThis layout was used on a chip that DID NOT work; it had ESD-induced latch-up This pad latched up at the arrows. The lack of guard rings was the problem. This cost all layer changes to all chips that used this pad.
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ADC Analog to Digital Converter
LAYOUT
CURRENT MIRRORS
LAYOUT
CURRENT MIRRORS
LAYOUT
CURRENT MIRRORS
LAYOUT
CURRENT MIRRORS

DIFF PAIR WITH CURRENT MIRROR LOAD
LAYOUT
NOISE COUPLING
LAYOUT
SHIELDING
LAYOUT
FLOORPLANNING
LAYOUT
ESD PAD LAYOUT TEST

Which layout is better at preventing latch-up and why? A or latchB
LAYOUT
ESD PAD LAYOUT TEST

Which layout is better at preventing latch-up and why? A or B latch-
LAYOUT
LAYOUT TEST
LAYOUT
ESD PAD LAYOUT TEST
Thanks for all your help; Nephi Spencer Lupe Badilla Tia Stoes Mark Judisack Trace Ponniah
LAYOUT
When you hit the Add button You get this pop up: When you hit this you get The Property mismatched Then hit this and all the cap Sizes come up as wrong Sizes because the tool is confused
The tool has a problem with lots of caps in the same block, it gets confused about sizes. The way we fix this is by Putting in the .eqv file this statement Match_by_property = true See next page for example
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Layout Reference Guide

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Layout Class 4 reference book

Layout Class 4 reference book

CAPACITORS TOP PLATE BOTTOM PLATE

CAPACITORS finding area

reading the schematic for a cap

This is metal options

This is a probe pad

reading the schematic for a cap

how to run an LVS JOB

the next pages are step by step on how to do pcf_files

Pads are along the white edge pads

How_to_Create_a pcf_File, continued

Filling out CN, continued p. Description (Details)

How_to_Create_a pcf_File, continued

skinny 120/121 117 90k/120k/121k 136

The command to run the prune is iss_verify with the p option.

How do I prune a net?

Too generate a parasitic netlist run:

Below is an example of a parasitic avanti_hercules run:

how to reference a library

how to reference a library

This tells you how to put in the name of the library

how to reference a library

how to reference a library

Now the library shows up in The design manager

equiv a = a {detect_permutable_ports = TRUE}

DETECT_PERMUTABLE_PORTS Port Swappability

DETECT_PERMUTABLE_PORTS Port Swappability

DETECT_PERMUTABLE_PORTS Port Swappability

DETECT_PERMUTABLE_PORTS Port Swappability

DETECT_PERMUTABLE_PORTS Port Swappability

DETECT_PERMUTABLE_PORTS Port Swappability

Old .eqv file without statement in it This was NOT CLEAN

This is the CLEAN .eqv file Notice the statement

Go to your working directory

Then cd into your project directory in this case D5AB0canc0

Your working area; this case chipD5AB0

Then cd into .snapshot

Then copy the snapshot to the corrupt cell and replace it

- pipe that concatenates two commands together ls * | more

u How do I copy one cell from one library to another

u How do I copy one cell from one library to another

u How do I copy one cell from one library to another

u How do I copy one cell from one library to another

u How do I copy one cell from one library to another

How do I reference a td library?

How do I stream data into an existing Virtuoso database?

This is a two set process. Step 1: 1. Open layoutPlus (lplus)

How do I stream in a GDS file from the UNIX command line.

This tells me it ran

how to view the xor changes

how to view the xor changes

how to view the xor changes

guard ring creation capability to 160k

--tsmc = process Follow the streamout checklist for a successful streamout

Put together by Lupe Badilla

Derivative Hierarchy Checklist

Derivative Hierarchy Checklist

Put togeather by Lupe Badilla

What is a master cell?

Example: DEBF0_MASTER, C5AF0_MASTER

C5AF3 C5AF4 C5AF5 C5AF6 -- Derivation Level

C5AF0 -- base level