CSE477 VLSI Digital Circuits Fall 2002 Lecture 08: MOS & Wire Capacitances

Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

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Review: Delay Definitions

Vin Vin
Propagation delay input waveform
50%

Vout

tp = (tpHL + tpLH )/2 t

90% 50% 10%

tpHL Vout
output waveform

tpLH

signal slopes

tf
CSE477 L08 Capacitance.2

tr

t
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CMOS Inverter: Dynamic

Transient, or dynamic, response determines the maximum speed at which a device can be operated.
VDD

Todays focus

Vout = 0 Rn CL

tpHL = f(Rn, CL)

Vin = V DD

Next lectures focus

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Sources of Capacitance
Vin Vout CL Vout2

M2

CG4 CDB2 Vout Cw CG3

M4

Vin

Vout2
M3

CGD12
M1

CDB1

intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance
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MOS Intrinsic Capacitances

Structure Channel

capacitances

capacitances

Depletion

regions of the reversebiased pn-junctions of the drain and source

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MOS Structure Capacitances

lateral diffusion Source n+ Poly Gate xd Ldrawn tox n+ xd Drain W n+

Top view

n+

Leff

Overlap capacitance (linear) CGSO = CGDO = Cox xd W = Co W

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MOS Channel Capacitances

The gate-to-channel capacitance depends upon the operating region and the terminal voltages
G
VGS +

CGS = CGCS + CGSO

S

CGD = CGCD + CGDO

D

n+

n+

n channel

CGB = CGCB

p substrate

depletion region

B
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Review: Summary of MOS Operating Regions

Cutoff (really subthreshold) VGS VT

q

Exponential in VGS with linear VDS dependence ID = IS e (qV GS /nkT) (1 - e -(qV DS /kT) ) (1 - VDS ) where n 1

Strong Inversion VGS > VT

q

Linear (Resistive) VDS < VDSAT = VGS - VT

ID = k W/L [(VGS VT)VDS VDS 2/2] (1+ VDS ) (VDS )

Saturated (Constant Current) VDS VDSAT = VGS - VT

IDSat = k W/L [(VGS VT)VDSAT VDSAT 2/2] (1+ VDS ) (VDSAT )

VT0 (V) NMOS PMOS

CSE477 L08 Capacitance.8

(V0.5 ) 0.4 -0.4

VDSAT (V) 0.63 -1

k(A/V2) 115 x 10-6 -30 x 10-6

(V-1 ) 0.06 -0.1

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0.43 -0.4

Average Distribution of Channel Capacitance

Operation Region Cutoff Resistive Saturation CGCB Cox WL 0 0 CGCS 0 Cox WL/2 (2/3)Cox WL CGCD 0 Cox WL/2 0 CGC Cox WL Cox WL CG Cox WL + 2CoW Cox WL + 2CoW

(2/3)Cox WL (2/3)Cox WL + 2CoW

Channel capacitance components are nonlinear and vary with operating voltage Most important regions are cutoff and saturation since that is where the device spends most of its time
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MOS Diffusion Capacitances

The junction (or diffusion) capacitance is from the reverse-biased source-body and drain-body pn-junctions.
G
VGS

S
-

n+

n+ depletion region

n channel

p substrate

CSB = CSdiff
B
CSE477 L08 Capacitance.10

CDB = CDdiff

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Source Junction View

channel-stop implant (NA+) W junction depth source bottom plate (ND) channel side walls substrate (NA)

xj

LS Cdiff = Cbp + Csw = Cj AREA + Cjsw PERIMETER = Cj LS W + Cjsw (2LS + W)

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Review: Reverse Bias Diode

All diodes in MOS digital circuits are reverse the dynamic response of the diode determined by depletion-region charge or junction capacitance Cj = Cj0 /((1 VD)/ 0)m

biased; + is
VD -

where Cj0 is the capacitance under zero-bias conditions (a function of physical parameters), 0 is the built-in potential (a function of physical parameters and temperature) and m is the grading coefficient
q q

m = for an abrupt junction (transition from n to p-material is instantaneous) m = 1/3 for a linear (or graded) junction (transition is gradual)

Nonlinear dependence (that decreases with increasing reverse bias)

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Junction Capacitance

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Reverse-Bias Diode Junction Capacitance

2 1 .5 1 0 .5 0 -5

abrupt (m=1/2)

Cj (fF)

linear (m=1/3)
-4 -3 -2 -1 0 1

Cj0

VD (V)
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MOS Capacitance Model

CGS = CGCS + CGSO CGS S CSB CSB = CSdiff

CGD = CGCD + CGDO CGD D CGB CDB CDB = CDdiff

B CGB = CGCB

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Transistor Capacitance Values for 0.25

Example: For an NMOS with L = 0.24 m, W = 0.36 m, LD = LS = 0.625 m CGSO = CGDO = Cox xd W = Co W = CGC = Cox WL = so Cgate_cap = CoxWL + 2CoW = Cbp = Cj LS W = Csw = Cjsw (2LS + W) = so Cdiffusion_cap =
Cox NMOS PMOS 6 6 Co 0.31 0.27 Cj 2 1.9 mj
b

Cjsw
(fF/ m)

mjsw 0.44 0.32

bw s

(fF/ m2) (fF/ m) (fF/ m2)

(V)

(V)

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0.5 0.9 0.48 0.9

0.28 0.22

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0.9 0.9

Transistor Capacitance Values for 0.25

Example: For an NMOS with L = 0.24 m, W = 0.36 m, LD = LS = 0.625 m CGSO = CGDO = Cox xd W = Co W = 0.11 fF CGC = Cox WL = 0.52 fF so Cgate_cap = CoxWL + 2CoW = 0.74 fF Cbp = Cj LS W = 0.45 fF Csw = Cjsw (2LS + W) = 0.45 fF so Cdiffusion_cap = 0.90 fF
Cox NMOS PMOS 6 6 Co 0.31 0.27 Cj 2 1.9 mj
b

Cjsw
(fF/ m)

mjsw 0.44 0.32

bw s

(fF/ m2) (fF/ m) (fF/ m2)

(V)

(V)

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0.5 0.9 0.48 0.9

0.28 0.22

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0.9 0.9

Review: Sources of Capacitance

Vin Vout CL CG4
M4

Vout2

M2

Vin

CGD12

pdrain ndrain

CDB2 CDB1

Vout Cw CG3
M3

Vout2

M1

intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance
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Gate-Drain Capacitance: The Miller Effect

M1 and M2 are either in cut-off or in saturation. The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor).
CGD1 Vin
M1

Vout V V Vin
M1

Vout

2CGB1

A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value
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Drain-Bulk Capacitance: Keq s (for 2.5 m)

We can simplify the diffusion capacitance calculations even further by using a Keq to relate the linearized capacitor to the value of the junction capacitance under zero-bias Ceq = Keq Cj0

high-to-low Keqbp Keqsw NMOS PMOS 0.57 0.79 0.61 0.86

low-to-high Keqbp Keqsw 0.79 0.59 0.81 0.7

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Extrinsic (Fan-Out) Capacitance

The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4. Cfan-out = Cgate (NMOS) + Cgate (PMOS) = (CGSOn + CGDOn + WnLnCox ) + (CGSOp + CGDOp + WpLpCox )

Simplification of the actual situation

q

Assumes all the components of Cgate are between Vout and GND VDD )

(or

Assumes the channel capacitances of the loading gates are constant

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Layout of Two Chained Inverters

VDD

PMOS 1.125/0.25
1.2 m =2 In Out Metal1

Polysilicon

0.125
NMOS 0.375/0.25
GND

0.5

W/L NMOS 0.375/0.25 PMOS 1.125/0.25

AD ( m2) PD ( m) AS ( m2) PS ( m) 0.3 0.7 1.875 2.375 0.3 0.7 1.875 2.375

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Components of CL (0.25 m)
C Term CGD1 CGD2 CDB1 CDB2 CG3 CG4 Cw CL Expression 2 Con Wn 2 Cop Wp Keqbpn ADnCj + Keqswn PDnCjsw Keqbpp ADpCj + Keqswp PDpCjsw (2 Con )Wn + Cox WnLn (2 Cop )Wp + Cox WpLp from extraction Value (fF) Value (fF) HL LH 0.23 0.23 0.61 0.66 1.5 0.76 2.28 0.12 6.1 0.61 0.90 1.15 0.76 2.28 0.12 6.0

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Wiring Capacitance

The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates. Wiring capacitance is growing in importance with the scaling of technology.

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Parallel Plate Wiring Capacitance

current flow L electrical field lines W H tdi dielectric (SiO2) substrate permittivity constant (SiO2= 3.9)
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Cpp = ( WL

d i

/tdi )
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Permittivity Values of Some Dielectrics

Material Free space Teflon AF Aromatic thermosets (SiLK) Polyimides (organic) Fluorosilicate glass (FSG) Silicon dioxide Glass epoxy (PCBs) Silicon nitride Alumina (package) Silicon
d i

1 2.1 2.6 2.8 3.1 3.4 3.2 4.0 3.9 4.5 5 7.5 9.5 11.7

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Sources of Interwire Capacitance

Cwire = Cpp + Cfringe + Cinterwire = ( + (
fringe interwire pp
d i

/tdi )WL
d i

+ (2
d i

)/log(tdi /H)

/tdi )HL

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Impact of Fringe Capacitance

H/tdi = 1 H/tdi = 0.5 Cpp

W/tdi
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(from [Bakoglu89])
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Impact of Interwire Capacitance

(from [Bakoglu89])
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Insights

For W/H < 1.5, the fringe component dominates the parallel-plate component. Fringing capacitance can increase the overall capacitance by a factor of 10 or more. When W < 1.75H interwire capacitance starts to dominate Interwire capacitance is more pronounced for wires in the higher interconnect layers (further from the substrate) Rules of thumb
q q q q

Never run wires in diffusion Use poly only for short runs Shorter wires lower R and C Thinner wires lower C but higher R

Wire delay nearly proportional to L2

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Wiring Capacitances
Poly Al1 Al2 Al3 Al4 Al5 Field 88 54 30 40 13 25 8.9 18 6.5 14 5.2 12 Active Poly Al1 Al2 Al3 Al4

41 47 15 27 9.4 19 6.8 15 5.4 12 Poly

57 54 17 29 10 20 7 15 5.4 12 Al1 95

pp in aF/ m2 fringe in aF/ m

36 45 15 27 8.9 18 6.6 14 Al2 85

41 49 15 27 9.1 19 Al3 85

35 45 14 27 Al4 85

38 52 Al5 115
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Interwire Cap
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40

per unit wire length in aF/ m for minimally-spaced wires

Dealing with Capacitance

Low capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO2
q q q

family of materials that are low-k dielectrics must also be suitable thermally and mechanically and compatible with (copper) interconnect

Copper interconnect allows wires to be thinner without increasing their resistance, thereby decreasing interwire capacitance SOI (silicon on insulator) to reduce junction capacitance

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Next Time: Dealing with Resistance

MOS structure resistance - Ron Wiring resistance Contact resistance

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Next Lecture and Reminders

Next lecture
q

MOS resistance
- Reading assignment Rabaey, et al, 4.3.2, 4.4.1-4.4.4

Reminders
q q q q q

Lecture lectures 9+10 will be combined on the 26th HW2 due today Project specifications dues October 3rd HW3 due Oct 10th Evening midterm exam scheduled
- Wednesday, October 16th from 8:15 to 10:15pm in 260 Willard - Only one midterm conflict filed for so far

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