CS122: Computer Architecture & Organization

Semester I, 2011

AMD dual-core Opteron

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Contact Information
Course in Charge: Prof. Viraj Kumar Assistant Professor

Viraj.Kumar@niituniversity.in

Office hours: Thursday 9:30am to 10:30am and by email MPs released on Thursday, (usually) due next Thursday MP 1 will be released this Thursday A word on the cheating policy Nothing will be graded until complete the Academic Integrity feedback on Moodle

Graded work
Five or six MPs, builds towards a Course Project, 30% of grade Except for the Course Project, you must work individually Submit something that can be tested 48 hours before the deadline Ill email you feedback (using an auto-grader) within 24 hours You can resubmit for full credit by the deadline Two Midterms: 12/9 (15%) ; 31/10 (20%) Final, cumulative, 21/12 (30%) Lab Work: 5%

What is computer architecture about?

Computer architecture is about building and analyzing computer systems HLL
Compiler

ASM

Processor

Memory

Input/Output

Instruction Set Architecture is bridge between hardware and software Study the MIPS ISA in detail Learn what compilers do when they translate high-level code into assembly (we wont learn how they do it) Learn how HLL program constructs are represented to the machine Key techniques: Pipelining, Caching, Virtual Memory Tuning complex code for performance (course project) Exploiting parallelism Prof. Kumar, Today I interviewed at Microsoft. Hey I used concepts learned in class multiple times. I just wanted to say THANKS!
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Multi-Core Processors
Two (or more) complete processors, fabricated on the same silicon chip Execute instructions from two (or more) programs/threads at same time

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XBox360: 3 PowerPC cores Sony PS 3: asymmetric 9 cores

IBM Power5

Why Multi-cores Now?

Number of transistors we can put on a chip growing exponentially

Performance vs. Power trade-off

Power has become a limiting factor for single cores hence multi-cores
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As programmers, do we care?
What happens if we run a program on a multi-core? void array_add(int A[], int B[], int C[], int length) { int i; for (i = 0 ; i < length ; ++i) { C[i] = A[i] + B[i]; } }

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Instruction set architectures

Software

ISA
Hardware

The ISA is an interface between software and hardware the hardware promises to implement all ISA instructions the software uses ISA primitives to build complex programs The instruction set architecture affects the hardware design simple ISAs require simpler, cheaper processors Also affects software design simple ISAs result in longer programs
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Why MIPS?
We study the MIPS instruction set architecture to illustrate concepts in assembly language and machine organization concepts are not MIPS-specific MIPS is just convenient because it is real, yet simple (unlike x86) MIPS ISA is used in many places, primarily in embedded systems routers from Cisco game machines like the Nintendo 64 and Sony Playstation 2

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What you will need to learn for Exam 1

You must become fluent in MIPS assembly: Translate from C++ to MIPS and MIPS to C++ Example: Translate the following recursive C++ function into MIPS int pow(int n, int m) { if (m == 1) return n; return n * pow(n, m-1); } How are complex expressions broken into simple instructions? How is recursion done? How are arguments passed? How are values returned?

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MIPS: register-to-register, three address

MIPS is a register-to-register, or load/store, architecture destination and sources of instructions must all be registers special instructions to access main memory (later) MIPS uses three-address instructions for data manipulation each ALU instruction contains a destination and two sources For example, an addition instruction (a = b + c) has the form: operation add a, destination operands b, sources c

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MIPS register file

MIPS processors have 32 registers, each of which holds a 32-bit value register addresses are 5 bits long More registers might seem better, but there is a limit to the goodness: more expensive: because of registers themselves, plus extra hardware like muxes to select individual registers instruction lengths may be affected 32
D data 5 Write D address 32 32 Register File 5 A address A data 32 B address B data 32 5

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MIPS register names

MIPS register names begin with a $. There are two naming conventions: by number: $0 $1 $2 $31

by (mostly) two-character names, such as: $a0-$a3 $s0-$s7 $t0-$t9 $sp $ra

Not all of the registers are equivalent: e.g., register $0 or $zero always contains the value 0 some have special uses, by convention ($sp holds stack pointer) You have to be a little careful in picking registers for your programs for now, stick to the registers $t0-$t9

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Basic arithmetic and logic operations

The basic integer arithmetic operations include the following: add sub mul div

And here are a few bitwise operations: and or xor nor

Remember that these all require three register operands; for example:
add $t0, $t1, $t2 mul $s1, $s1, $a0 # $t0 = $t1 + $t2 # $s1 = $s1 x $a0

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Larger expressions
Complex arithmetic expressions may require multiple MIPS operations Example: t0 = (t1 + t2) (t3 t4)
# $t0 contains $t1 + $t2 # temp value $t6 = $t3 - $t4 # $t0 contains the final product

add $t0, $t1, $t2 sub $t6, $t3, $t4 mul $t0, $t0, $t6

Temporary registers may be necessary, since each MIPS instructions can access only two source registers and one destination in this example, we could re-use $t3 instead of introducing $t6 must be careful not to modify registers that are needed again later

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How are registers initialized?

Special MIPS instructions allow you to specify a signed constant, or immediate value, for the second source instead of a register e.g., here is the immediate add instruction, addi:
addi $t0, $t1, 4 # $t0 = $t1 + 4

Immediate operands can be used in conjunction with the $zero register to write constants into registers:
addi $t0, $0, 4 $t0, 4 # $t0 = 4 # $t0 = 4

Shorthand:

li
(pseudo-instruction)

MIPS is still considered a load/store architecture, because arithmetic operands cannot be from arbitrary memory locations. They must either be registers or constants that are embedded in the instruction.
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Our first MIPS program

Lets translate the following C++ program into MIPS: void main() { int i = 516; int j = i*(i+1)/2; i = i + j; } main: li $t0, 516 addi $t1, $t0, mul $t1, $t0, li $t2, 2 div $t1, $t1, add $t0, $t0, jr $ra

1 $t1 $t2 $t1

# # # #

start of main i = 516 i + 1 i * (i + 1)

# j = i*(i+1)/2 # i = i + j # return

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Translate this program into MIPS

Program to swap two numbers without using a temporary: void main() { int i = 516; int j = 615; i = i ^ j; // ^ = bitwise XOR j = i ^ j; i = i ^ j; }

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Instructions
MIPS assemblers support pseudo-instructions give the illusion of a more expressive instruction set actually translated into one or more simpler, real instructions Examples li (load immediate) and move (copy one register into another) You can always use pseudo-instructions on assignments and on exams For now, well focus on real instructions how are they encoded? Answer: As a sequence of bits Instruction fetch (machine language) Instruction decode Data fetch The control unit sits inside an endless loop: Execute Result store
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MIPS instructions
MIPS machine language is designed to be easy to fetch and decode: each MIPS instruction is the same length, 32 bits only three different instruction formats, with many similarities format determined by its first 6 bits: operation code, or opcode Fixed-size instructions: (+) easy to fetch/pre-fetch instructions ( )limits number of operations, limits flexibility of ISA Small number of formats: (+) easy to decode instructions (simple, fast hardware) ( )limits flexibility of ISA Studying MIPS machine language will also reveal some restrictions in the instruction set architecture, and how they can be overcome.
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R-type format
Register-to-register arithmetic instructions use the R-type format opcode 6 bits Six rs 5 bits rt 5 bits rd 5 bits shamt 5 bits func 6 bits

different fields: opcode is an operation code that selects a specific operation rs and rt are the first and second source registers rd is the destination register shamt is only used for shift instructions func is used together with opcode to select an arithmetic instruction

The inside back cover of the textbook lists opcodes and function codes for all of the MIPS instructions
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MIPS registers
We have to encode register names as 5-bit numbers from 00000 to 11111 e.g., $t8 is register $24, which is represented as 11000 The number of registers available affects the instruction length: R-type instructions references 3 registers: total of 15 bits Adding more registers either makes instructions longer than 32 bits, or shortens fields like opcode (reducing number of available operations)

opcode
squeezed

rs
wide

rt
wide

rd
wide

shamt 5 bits

func
squeezed

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I-type format
Used for immediate instructions, plus load, store and branch opcode 6 bits rs 5 bits rt 5 bits immediate 16 bits

For uniformity, opcode, rs and rt are located as in the R-format The meaning of the register fields depends on the exact instruction: rs is always a source register (memory address for load and store) rt is a source register for store and branch, but a destination register for all other I-type instructions The immediate is a 16-bit signed twos-complement value. It can range from -32,768 to +32,767. Question: How does MIPS load a 32-bit constant into a register? Answer: Two instructions. Make the common case fast.
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Branches
Two branch instructions: beq $t0, $t1, label bne $t0, $t1, label 000100 op 10001 rs

# if t0 == t1, jump to label # if t0 != t1, jump to label 10010 rt 0000 0000 0000 0010 address (offset)

For branch instructions, the constant field is not an address, but an offset from the next program counter (PC+4) to the target address.
beq add addi add $t0, $t0, $t1, $v1, $t1, $t0, $t0, $v0, EQ $t1 $0 $v0

EQ:

Since the branch target EQ is two instructions past the instruction after beq, the address field contains 2
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J-type format
In real programs, branch targets are less than 32,767 instructions away branches are mostly used in loops and conditionals programmers are taught to make loop bodies short For far jumps, use j and jal instructions (J-type instruction format) opcode 6 bits address (exact) 26 bits

address is always a multiple of 4 (32 bits per instruction) only the top 26 bits actually stored (last two are always 0) For even longer jumps, the jump register (jr) instruction can be used.
jr $ra # Jump to 32-bit address in register $ra

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Pseudo-branches
The MIPS processor only supports two branch instructions, beq and bne, but to simplify your life the assembler provides the following other branches:
blt ble bgt bge $t0, $t0, $t0, $t0, $t1, $t1, $t1, $t1, L1 L2 L3 L4 // // // // Branch Branch Branch Branch if if if if $t0 $t0 $t0 $t0 < $t1 <= $t1 > $t1 >= $t1

There are also immediate versions of these branches, where the second source is a constant instead of a register. Later this semester well see how supporting just beq and bne simplifies the processor design.

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