Basic Computer Organization CH-4

Richard Gomez 6/14/01 Computer Science

Quote: John Von Neumann If people do not believe that mathematics is simple,

it is only because they do not realize how complicated life is.

3 Fundamental Components of Computer

The CPU (ALU, Control Unit, Registers) The Memory Subsystem (Stored Data) The I/O subsystem (I/O devices)

CPU

Address Bus Data Bus

Control Bus

Memory Subsystem

I/O Device Subsystem

Each of these Components are connected through Buses.

BUS - Physically a set of wires. The components of the Computer are connected to these buses. Address Bus Data Bus Control Bus

Address Bus
Used to specify the address of the memory location to access. Each I/O devices has a unique address. (monitor, mouse, cd-rom) CPU reads data or instructions from other locations by specifying the address of its location. CPU always outputs to the address bus and never reads from it.

Data Bus
Actual data is transferred via the data bus. When the cpu sends an address to memory, the memory will send data via the data bus in return to the cpu.

Control Bus
Collection of individual control signals. Whether the cpu will read or write data. CPU is accessing memory or an I/O device Memory or I/O is ready to transfer data

I/O Bus or Local Bus

In todays computers the the I/O controller will have an extra bus called the I/O bus. The I/O bus will be used to access all other I/O devices connected to the system. Example: PCI bus

Instruction Cycles
Procedure the CPU goes through to process an instruction. 1. Fetch - get instruction 2. Decode - interperate the instruction 3. Execute - run the instruction.

Process of an Instruction (Define fetch)

When CPU is ready the it will assert the read control signal. Depending on the CPU the read can be active high (1) or low (0). After being asserted the subsystem will return the data through the data bus. The CPU will then receive this data and store into one of its registers

Process of an Instruction (Define Decode)

Now the CPU will decode the instruction. The CPU will determine the sequences of commands needed to perform. Each instruction can require different sequences of operations. This is perform within the CPU with no system buses.

Process of an Instruction (Define Execute)

The CPU will now execute the instruction. This sequence will vary from different instructions. Read or write data to memory or I/O subsystem.

Timing Diagram: Memory Read

Address is placed at beginning of clock after one clock cycle the CPU asserts the read. Causes the memory to place its data onto the data bus. CLK : System Clock used to synchronize CLK

Bus
Bus Read

Address
Data

Timing Diagram : Memory Write

CPU places the Address and data on the first clock cycle. At the start of the second clock the CPU will assert the write control signal. This will then start memory to store data. After some time the write is then deasserted by the CPU after removing the address and data from the subsystem. CLK Address Bus Data Bus
Address Data

Read

I/O read and Write Cycles

The I/O read and Write cycles are similar to the memory read and write. Memory mapped I/O : Same sequences as input output to read and write. The processor treats an I/O port as a memory location. This results in the same treatment as a memory access.

CPU organization
CPU controls the Computer The CPU will fetch, decode and execute instructions. The CPU has three internal sections: register section, ALU and Control Unit

Register Section
Includes collection of registers and a bus. Processors instruction set architecture are found in this section. Non accessible registers by the programmer. These are to be used for registers to latch the address being accessed and a temp storage register.

Arithmetic/Logic Unit (ALU)

Performs most Arithmetic and logical operations. Retrieves and stores its information with the register section of the CPU.

Memory Subsystem

2 Types of Memory:
ROM : Read Only Memory

Program that is loaded into memory and cannot be changed also retains its data even without power. Also called read/write memory. This type of memory can have a program loaded and then reloaded. It also loses its data with no power.

RAM : Random Access Memory

Different ROM Chips

Masked ROM :

ROM that is programmed with data when fabricated. Data will not change once installed. Hardwired.

Programmable ROM (PROM) :

Capable of being programmed by the user with a ROM programmer. Not hardwired. Much like the PROM this EPROM can be programmed and then erased by light.
Another form of EPROM but is reprogammable

Erasable PROM (EPROM) :

EEPROM :

Different RAM Chips

Dynamic RAM (DRAM) :

Leaky capacitors. Caps are charged and slowly leak until they are refreshed to there original data locations. Ex. Computer RAM Much like a register. The contents stay valid and does not have to be refreshed. SRAM is faster than DRAM but cost more Ex. Cache

Static RAM (SRAM) :

Each RAM chip has 2^n * m. n address inputs and m bidirectional data pins

Internal Memory Organization

ROM and RAM have similar internal organization. Internal linear Organization. Ex. 8 X 2 ROM Chip:
0 0 1 2 3 4 5 6 7

A2
A1 A0

0 1 2 Decoder 3 4 5 6 E 7 3-8

1 2 3 4 5 6 7

CE OE

D0

Internal Memory Cont.

This chip has 3 Address inputs 2 data outputs 16 bits of internal storage arranged as 8 2-bit locations The 3 address bits will be decoded to select one of the 8 locations only if CE is active (1). With both CE and OE enabled the buffers are enabled and data is allowed to flow out.

Internal Memory Cont.

As the # of locations increases the size of the address decoder needed in linear organization becomes very large. To get around this problem we can use multi-dimensions of decoding. The size of an n to 2^n decoder is said to be O(2^n)

Memory Subsystem
Memory subsystem is the combination of memory chips Example : 8 x 2 chips can be combined to make an 8 x 4 memory. Both chips will receive the same 3 address inputs from the bus, as well as the CE and OE signals. The data pins of the first chip are connected to bits 3 and 2 and the other to 1 an 0 of the data bus

Memory Subsystem Cont.

When the CPU reads data it places the address on the address bus. Both chips will read in bits A1, A2, and A0 and decode Since both chips are using the same CE and OE either both chips are active or not. To the CPU it will act just like an 8 x 4 memory chip.

Von Neumann and Harvard architectures

Are similar in implementation using this diagram.

Address Bus
Data Bus Control Bus CPU Memory Subsystem

I/O Device Subsystem

They differ in how data is arranged in memory. The Neumann uses mixed memory module while the Harvard uses separate memory modules for data and instructions

Von Neumann and Harvard architectures

Modern computers today predominantly use the Neumann architecture. Although it will also use some elements of the harvard architecture. The difference is the PC will assign sections of memory to either instructions or data.
Although this is not a true Harvard architecture because that system requires that a memory module always be assign the same one of the two.