Chap. 5 Basic Computer Org.

and Design

5-1

5-1 Instruction Codes

The user of a computer can control the process by means of a program A program is a set of instructions that specify the operations, operand, the

Instruction Cycle

sequence(control) A instruction is a binary code that specifies a sequence of microoperations Instruction codes together with data are stored in memory(=Stored Program Concept) The computer reads each instruction from memory and places it in a control register. The control then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of microoperations. Instruction Code :

A group of bits that instruct the computer to perform a specific operation It is usually divided into parts(refer to Fig. 5-1 instruction format) Instruction Format

15 12 11 0 Operation Code : Op. Code Address The most basic part of an instruction code A group of bits that define such operations as add, subtract, multiply, shift, and complement(bit 12-15 : 24 = 16 distinct operations)
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Stored Program Organization : Fig. 5-1 The simplest way to organize a computer
One processor register : AC(Accumulator)

The operation is performed with the memory operand and the content of AC Op. Code : specify 16 possible operations(4 bit) Address : specify the address of an operand(12 bit) If an operation in an instruction code does not need an operand from memory, the rest of the bits in the instruction(address field) can be used for other purpose( 16 instruction : Tab. 5-2 , 25 instruction) Store each instruction code(program) and operand (data) in 16-bit memory word

Instruction code format with two parts : Op. Code + Address Exam) Clear AC, Increment AC, Complement AC, ...

Memory : 12 bit = 4096 word(Instruction and Data are stored)

Addressing Mode Immediate operand address :

the second part of an instruction code(address field) specifies an operand

Direct operand address : Fig. 5-2(b)

the second part of an instruction code specifies the address of an operand

Indirect operand address : Fig. 5-2(c)

the bits in the second part of the instruction designate an address of a memory word in which the address of the operand is found (Pointer )

I=0 : Direct, I=1 : Indirect

One bit of the instruction code is used to distinguish between a direct and an indirect address : Fig. 5-2(a)
Chap. 5 Basic Computer Organization and Design Dept. of Info. Of Computer

Computer System Architecture

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Effective Address The operand address in computation-type instruction or the target address in a branch-type instruction

5-2 Computer Registers

List of Registers for the Basic Computer : Tab. 5-1 Basic computer registers and memory : Fig. 5-3 Data Register(DR) : hold the operand(Data) read from memory Accumulator Register(AC) : general purpose processing register Instruction Register(IR) : hold the instruction read from memory Temporary Register(TR) : hold a temporary data during processing Address Register(AR) : hold a memory address, 12 bit width Program Counter(PC) :
hold the address of the next instruction to be read from memory after the current instruction is executed Instruction words are read and executed in sequence unless a branch instruction is encountered A branch instruction calls for a transfer to a nonconsecutive instruction in the program The address part of a branch instruction is transferred to PC to become the address of the next instruction To read instruction, memory read cycle is initiated, and PC is incremented by one(next instruction fetch)

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5-4

Input Register(INPR) : receive an 8-bit character from an input device Output Register(OUTR) : hold an 8-bit character for an output device

Common Bus System The basic computer has eight registers, a memory unit, and a control unit(in Sec. 5-4) Paths must be provided to transfer information from one register to another and between memory and registers A more efficient scheme for transferring information in a system with many registers is to use a common bus(in Sec. 4-3) The connection of the registers and memory of the basic computer to a common bus system : Fig. 5-4
The outputs of seven registers and memory are connected to the common bus The specific output is selected by mux(S0, S1, S2) :

Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6) Device AC INPR OUTR mux memory register bus When LD(Load Input) is enable, the particular register receives the data from the bus

Control Input : LD, INC, CLR, Write, Read Address Register : Address bus ( Bus address data )

AC DR memory read (p. 146, LDA ) Memory write AC write (p. 147, STA ) Chap. 5 Basic Computer Organization and Design Dept. of Info. Of Computer

Computer System Architecture

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Accumulator(AC) : 3 Path

1) Register Microoperation : clear AC, shfift AC, 2) Data Register : add DR to AC, and DR to AC( AC End carry bit set/reset), memory READ(DR ) 3) INPR : Device (Adder & Logic )

s2 s1 s0 Memory unit 409616 Address

Bus 7

Write AR
LD INR

Read

CLR

PC
LD INR CLR

Note) Two microoperations can be executed s s s 100 (4), DR (load ) DR AC : at the same time
2 1 0

DR
LD INR CLR

AC DR : DR Adder & Logic AC (load )

Adder and logic

E AC
LD INR CLR

INPR

IR
LD

TR
LD INR CLR

OUTR
LD

Clock

16-bit common bus

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Dept. of Info. Of Computer

5-6

5-3 Computer Instruction

3 Instruction Code Formats : Fig. 5-5 Memory-reference instruction
Opcode = 000 110

I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx

11 0

I=0 : Direct, I=1 : Indirect

15 14

12

I Opcode

Address

Register-reference instruction
7xxx (7800 ~ 7001) : CLA, CMA, .
15 14 12 11 0

Register Operation

Input-Output instruction
Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, .
15 14 12 11 0

Symbol AND ADD LDA STA BUN BSA ISZ CLA CLE CMS CME CIR CIL INC SPA SNA SZA SZE HLT INP OUT SKI SKO ION IOF

Hex Code I=0 I=1 0xxx 8xxx 1xxx 9xxx 2xxx Axxx 3xxx Bxxx 4xxx Cxxx 5xxx Dxxx 6xxx Exxx 7800 7400 7200 7100 7080 7040 7020 7010 7008 7004 7002 7001 F800 F400 F200 F100 F080 F040

Description And memory word to AC Add memory word to AC Load memory word to AC Store content of AC in memory Branch unconditionally Branch and Save return address Increment and skip if zero Clear AC Clear E Complement AC Complement E Circulate right AC and E Circulate left AC and E Increment AC Skip next instruction if AC positive Skip next instruction if AC negative Skip next instruction if AC zero Skip next instruction if E is 0 Halt computer Input character to AC Output character from AC Skip on input flag Skip on output flag Interrupt On Interrupt Off

I/O Operation

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If the computer includes a sufficient number of Instruction Set Completeness instructions in each of the following categories Arithmetic, Logical, and shift : CMA, INC, .. Moving information to and from memory and AC : STA, LDA Program control : BUN, BSA, ISZ Input/Output : INP, OUT

5-4 Timing and Control

Clock pulses A master clock generator controls the timing for all registers in the basic computer The clock pulses are applied to all F/Fs and registers in system The clock pulses do not change the state of a register unless the register is enabled by a control signal The control signals are generated in the control unit : Fig. 5-6
The control signals provide control inputs for the multiplexers in the common bus, control inputs in processor registers, and microoperations for the accumulator

Two major types of control organization Hardwired Control : Chap. 5

The control logic is implemented with gates, F/Fs, decoders, and other digital circuits + Fast operation, - Wiring change(if the design has to be modified)

Computer System Architecture

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Dept. of Info. Of Computer

5-8

Microprogrammed Control : Chap. 7

The control information is stored in a control memory, and the control memory is programmed to initiate the required sequence of microoperations + Any required change can be done by updating the microprogram in control memory, - Slow operation
Instruction register (IR)

Control Unit : Fig. 5-6

15

14

13

12

11 - 0

Control Unit = Control Logic Gate + 3 X 8 Decoder + Instruction Register + Timing Signal Timing Signal = 4 X 16 Decoder + 4-bit Sequence Counter Exam) Control timing : Fig. 5-7
Sequence Counter is cleared when D3T4 =1 : D3T4 : SC 0
I

38 decoder 7 6 5 4 3 2 1 0 D0

Other inputs

. . D7 .

Control logic gates

Control outputs

T15 T0 15 14
. . .

10

Memory R/W cycle time > Clock cycle time

, wait cycle .

416 decoder

. . .

4-bit sequence counter (SC)

Increment(INR) Clear(CLR) Clock

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Dept. of Info. Of Computer

. . .

5-9

Exam) Register transfer statement : T0 : AR PC A transfer of the content of PC into AR if timing signal T0 is active
1) During T0 active, the content of PC is placed onto the bus ( S2 S1S0 ) 2) LD(load) input of AR is enabled, the actual transfer occurs at the next positive transition of the clock(T0 rising edge clock) T0 : Inactive 3) SC(sequence counter) is incremented : 0000 (T0 ) 0000 (T1 ) T1 : Active

5-5 Instruction Cycle

Instruction Cycle 1) Instruction Fetch from Memory 2) Instruction Decode 3) Read Effective Address(if indirect addressing mode) 4) Instruction Execution 5) Go to step 1) : Next Instruction[PC + 1] Instruction Fetch : T0, T1(Fig. 5-8)
T0 : AR PC T1 : IR M [ AR], PC PC 1

Continue indefinitely unless HALT instruction is encountered

T0 = 1

T0 : AR PC

1) Place the content of PC onto the bus by making the bus selection inputs S2S1S0=010 2) Transfer the content of the bus to AR by enabling the LD input of AR
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5-10

T1 = 1

T1 : IR M [ AR], PC PC 1

1) Enable the read input memory 2) Place the content of memory onto the bus by making S2S1S0= 111 3) Transfer the content of the bus to IR by enable the LD input of IR 4) Increment PC by enabling the INR input of PC
T1=1 T0=1
Memory unit Memory unit s2 s1 s0

Instruction Decode : T2
T2 : D0 ,...., D7 Decode IR(12 14), AR IR(0 11), I IR(15)

Bus

Op.code

Address Di/Indirect
Address Read

0 1 0

1 1 1

IR(12-14) Fig. 5-6 D0 - D7

Instruction Execution : T3, T4, T5, T6

IR (12 14) 111

Read effective Register(I=0) D7IT3(Execute) Address I/O (I=1) D7IT3 (Execute) D7=0 : Memory Ref. Indirect(I=1) D7IT3( AR M [AR] ) Direct (I=0) nothing in T3 Register I/O T3 Memory Ref. T3 Operand effective address D7=1

AR
LD

PC
INR

IR
LD

Memory Ref. T4, T5, T6 : Fig. 5-11

Clock

Flowchart for instruction cycle(Initial Configuration) : Fig. 5-9

Computer System Architecture

Common bus

Chap. 5 Basic Computer Organization and Design

Dept. of Info. Of Computer

5-11

Register Ref. Instruction Address r = D7IT3 : IR(i) = Bi IR(0 -11) B0 - B11 : 12 Register Ref. Instruction (Tab. 5-3)

Fig. 5-9 Flowchart for instruction cycle(initial)

Start SC 0 T0 AR PC T1 IR M[AR], PC PC+1 T2 Decode operation code in IR(12-14) AR IR(0-11), I I(15)

5-6 Memory Ref. Instruction

D7 : Register or I/O = 1 = 111 D6 - D0 : 7 Memory Ref. Instruction(Tab. 5-4)
D0T4 : DR M [ AR] D0T5 : AC AC DR , SC 0
IR(12,13,14)

3X8 Decoder

(Register or I/O) = 1 I

0 = (Memory-reference

AND to AC
(I/O) = 1 I 0 = (register) (indirect) = 1 I 0 = (direct) T3 Execute input-output instruction SC 0 T3 Execute register-reference instruction SC 0 AR T3 M[AR] Nothing T3

ADD to AC
D1T4 : DR M [ AR] D1T5 : AC AC DR , E Cout , SC 0

Execute memory-reference instruction SC 0

LDA : memory read

D2T4 : DR M [ AR] D2T5 : AC DR , SC 0
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STA : memory write

D3T4 : M [ AR] AC, SC 0

Fig. 5-10 Example of BSA

PC = 10 PC = 21 0 BSA 135 next instruction

BUN : branch unconditionally

D4T4 : PC AR, SC 0

BSA : branch and save return address

D5T4 : M [ AR] PC, AR AR 1 D5T5 : PC AR, SC 0

135 21(return address) PC = 136 Subroutine 1 BUN 135

Return Address : save return address ( 135 21 ) D5T4 : M [135] 21( PC ), 136( AR) 135 1 Subroutine Call : Fig. 5-10
D5T5 : 136( PC ) 136( AR), SC 0

ISZ : increment and skip if zero

D6T4 : DR M [ AR] D6T5 : DR DR 1

D6T6 : M [ AR] DR , if ( DR 0) then ( PC PC 1), SC 0

Control Flowchart : Fig. 5-11 Flowchart for the 7 memory reference instruction
The longest instruction : ISZ(T6) 3 bit Sequence Counter ( 4 )
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Dept. of Info. Of Computer

5-13

5-7 Input-Output and Interrupt

Input-Output Configuration : Fig. 5-12 Input Register(INPR), Output Register(OUTR)
These two registers communicate with a communication interface serially and with the AC in parallel Each quantity of information has eight bits of an alphanumeric code

Input Flag(FGI), Output Flag(FGO)

FGI : set when INPR is ready( ), clear when INPR is empty FGO : set when operation is completed( ), clear when output device is in the process of printing

1 : Ready 0 : Not ready

Input-Output Instruction : Tab. 5-5 Address p = D7IT3 : IR(i) = Bi IR(6 -11) B6 - B11 : 6 I/O Instruction
Program Interrupt I/O Transfer Modes
1) Programmed I/O, 2) Interrupt-initiated I/O, 3) DMA, 4) IOP 2) Interrupt-initiated I/O (FGI FGO 1 Int. ) Maskable Interrupt ( ION IOF Int. mask )
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5-14

Interrupt Cycle : Fig. 5-13

During the execute phase, IEN is checked by the control

Instruction cycle

=0

=1

Interrupt cycle

IEN = 0 : the programmer does not want to use the interrupt, so control continues with the next instruction cycle IEN = 1 : the control circuit checks the flag bit, If either flag set to 1, R F/F is set to 1 R = 0 : instruction cycle R = 1 : Instruction cycle

Fetch and decode instruction

Store return address in location 0 M[0] PC =0

Execute instruction

IEN =1 =1

Branch to location 1 PC 1 FGI =0

At the end of the execute phase, control checks the value of R

R

=1

FGO =0

IEN R

0 0

Demonstration of the interrupt cycle : Fig. 5-14

The memory location at address 0 as the place for storing the return address Interrupt Branch to memory location 1 Interrupt cycle IEN=0 ( ISR Interrupt ISR ION )

The condition for R = 1 T0'T1'T2' ( IEN )( FGI FGO) : R 1 Modified Fetch Phase
Modified Fetch and Decode Phase
Interrupt Here

PC =

0 1

256(return address) 0 BUN 1120 Main Program

255 256

Save Return Address(PC) at 0 Jump to 1(PC=1)

RT0 : AR 0, TR PC RT1 : M [ AR] TR, PC 0 RT2 : PC PC 1, IEN 0, R 0, SC 0

Chap. 5 Basic Computer Organization and Design 1120 1 Interrupt Service Routine BUN 0

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Dept. of Info. Of Computer

5-15

5-8 Complete Computer Description

The final flowchart of the instruction cycle : Fig. 5-15 The control function and microoperation : Tab. 5-6

5-9 Design of Basic Computer

The basic computer consists of the following hardware components 1. A memory unit with 4096 words of 16bits 2. Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC(Fig. 2-11) 3. Seven F/Fs : I, S, E, R, IEN, FGI, and FGO 4. Two decoder in control unit : 3 x 8 operation decoder, 4 x 16 timing Section decoder(Fig. 5-6) 5. A 16-bit common bus(Fig. 5-4) 6. Control Logic Gates : Fig. 5-6 Box Control Output 7. Adder and Logic circuit connected to the AC input Control Logic Gates 1. Signals to control the inputs of the nine registers 2. Signals to control the read and write inputs of memory 3. Signals to set, clear, or complement the F/Fs 4. Signals for S2 S1 S0 to select a register for the bus 5. Signals to control the AC adder and logic circuit
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5-16

Register Control : AR Control inputs of AR : LD, INR, CLR AR ? Find all the statements that change the AR in Tab. 5-6 R ' T0 : AR PC Control functions R ' T1 : AR IR (0 11)
LD( AR) R' T0 R' T1 D7 ' IT3 D7 ' IT3 : AR M [ AR] CLR( AR) RT0 RT0 : AR 0 INR( AR) D5T4
D5T4 : AR AR 1

From Bus

12

AR

12 To Bus Clock

D'7 I T3 T2

LD

INR

CLR

R T0 D5 T4

Memory Control : READ M [ AR] ? Control inputs of Memory : READ, WRITE Find all the statements that specify a read operation in Tab. 5-6 Control function
READ R' T1 D7 ' IT3 ( D0 D1 D2 D3 )T4

? M [ AR]
J 0 1 KQ(t+1) 1 0 0 1

F/F Control : IEN IEN ? Control functions

pB7 : IEN 1 pB6 : IEN 0 RT2 : IEN 0
Computer System Architecture

D'7 I T3

B7 Clock B6 R T2

SET

Q
IEN

CLR

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Dept. of Info. Of Computer

5-17

Bus Control Encoder for Bus Selection : Tab. 5-7

S0 = x1 + x3 + x5 + x7 S1 = x2 + x3 + x6 + x7 S0 = x4 + x5 + x5 + x7

x1 = 1 : Bus AR Find ? AR
D T : PC AR 4 4

D5T5 : PC AR
Control Function : x1 D4T4 D5T5

x1 x2 x3 x4 x5 x6 x7

S0

Encoder

S1 S2

Multiplexer Bus Select Input

x2 = 1 : Bus PC Find ? PC

x7 = 1 : Bus Memory Find ? M [ AR]

Same as Memory Read Control Function : x7 R' T1 D7 ' IT3 ( D0 D1 D2 D3 )T4

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5-18

5-10 Design of Accumulator Logic

Circuits associated with AC : Fig. 5-19

Fig. 5-21
16 16

Fig. 2-11

From DR
8

From INPR

Adder and logic circuit

16

Accumulator register (AC)

16

To Bus

LD

INR

CLR Clock

Fig. 5-20

Control gates

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5-19

Control of AC : Fig. 5-20 Find the statement that change the AC : AC ?

From adder and logic 16 AC 16 To Bus Clock D0 AND
LD INR CLR

D0T5 : AC AC DR D1T5 : AC AC DR D2T5 : AC DR pB11 : AC (0 7) INPR rB9 : AC AC rB7 : AC shr AC , AC (15) E rB6 : AC shr AC , AC (0) E rB11 : AC 0 rB5 : AC AC 1
CLR INR LD

T5 D1 D2 T5 p B11 r B9 SHR B7 SHL B6 INC B5 CLR B11 COM INPR ADD

DR

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5-20

Adder and Logic Circuit : Fig. 5-21 ( 16 bit = 16 )

DR(i) AC(i)

(Output of OR gate in Fig. 5-20) AND Ci FA Ci+1 DR LD

J 0 1 KQ(t+1) 1 0 0 1

ADD

Ii (Fig.2-11)

AC(i)

From INPR bit(i)

INPR Clock COM

* Fig. 2-11 Increment, Clear, Count

SHR AC(i+1) SHL AC(i-1)

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Mano Machine

5-21

Integration !

Fig. 5-4 : Common Bus(p.130) Fig. 2-11 : Register(p. 59) Fig. 5-6 : Control Unit(p. 137) Fig. 5-16, 17,18 : Control Logic Gate(p.161- 163)
Fig. 5-4 Component Control Input Register, Memory, F/Fs, Bus Selection

Fig. 5-20 : AC control(p.165) Fig. 5-21 : Adder and Logic(p.166)

Due Date : 1

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