ARM7TDMI-S CPU

MultiMarket Semiconductors
BL Standard ICs - Microcontrollers
February 2004
 ARM Architecture

• Thumb state

• Instruction set

• Processor Modes

• Register usage

• Interrupt Handling

• 3-stage Pipeline

Semiconductors 2
 ARM7TDMI-S
The ARM7TDMI-S is based on ARM7 core
– 3 stage pipeline
– Von Neumann architecture
– CPI ~1.9
– T: Thumb instruction set
– D: includes debug extensions
– M: enhanced multiplier (32x8) with instructions for 64-bit
results
– I: core has EmbeddedICE logic extensions
– S: fully synthesisable (soft IP)

Semiconductors 3
 Thumb State

Semiconductors 4
 Thumb state
• ARM uses a 32-bit architecture with a subset of 16-bit
instructions, still using 32-bit data and registers.
• Set of instructions re-coded into 16 bits
– Improved code density by ~ 30%
– saving program memory space

• In Thumb state only the program code is 16-bit wide

– after fetching the 16-bit instructions from memory, they are de-
compressed to 32 bit instructions before they are decoded and
executed
– all operations are still 32-bit operations

Semiconductors 5
 ARM and Thumb Interworking
• Switch between ARM state and Thumb state using BX
instruction
– In ARM state: BX<condition> Rn
– In Thumb state: BX Rn
3 1 0
Rn 1
n: 0-15

ARM / Thumb
BX selection
0: ARM state
3 1 0 1: Thumb
Destinatio1 state
n 0
address
Semiconductors 6
 Instruction Set

Semiconductors 7
 ARM Instruction Set
• All instructions are 32-bits long
• Many instructions execute in a single cycle
• Most of the ARM Instructions can be conditionally executed
• Could be divided into six broad classes of instruction
– Branch instructions
– Data Processing instructions
– Status register transfer instructions
– Load and Store instructions
– Coprocessor instructions
– Exception-generating instructions

Semiconductors 8
 Thumb Instruction Set
• All instructions are 16-bits long

• Most of the Thumb Instructions cannot be conditionally executed

• Thumb instruction set is subset of ARM instruction set

• It takes more instructions in Thumb to do the same job in ARM resulting

in a performance penalty

Semiconductors 9
 Processor Modes

Semiconductors 10
 Processor Modes(1)
ARM has seven operating modes
– User unprivileged mode under which most applications
run
– FIQ entered, when a high priority (fast) interrupt is raised
– IRQ general purpose interrupt handling
– Supervisor protected mode for the operating system
entered on reset or software interrupt instruction
– System privileged mode using same registers as user mode
– Abort used to handle memory access violations
– Undefined used to handle undefined instructions

Semiconductors 11
 Processor Modes(2)

User
System
FIQ
IRQ
Privileged Modes Exception Modes
Supervisor
Abort
Undefined

Semiconductors 12
 Privileged and Exception Modes
FIQ IRQ Supervisor Abort Undefined

• Entered when a specific exception occurs

• Each mode has additional registers to prevent corruption

• On Reset ARM core is in Supervisor mode

• Have access to system resources

• Can change modes freely using ARM instructions

Semiconductors 13
 User Mode & System Mode
• User Mode:
– User mode has access to limited system resources
– Cannot change modes freely within User mode
– User program can make a supervisor call using the SWI
instruction(SWI- Software Interrupt but is usually called
Supervisor call)

• System Mode:
– System mode is similar to User mode but used by OS which
needs access to system resources (Privileged)
– System mode also used during nested interrupt handling

Semiconductors 14
 ARM Registers

Semiconductors 15
 Registers (1)
An ARM core has 37 registers (32-bits wide)
• General purpose registers
– 1 program counter
– 30 general purpose registers

• Status registers
– 1 current program status register(CPSR)
– 5 saved program status registers(SPSR)
These registers are not all accessible at the same time. The processor
state and operating mode determine which registers are available to the
programmer.

Semiconductors 16
 Registers (II)
• Depending on processor mode one of several banks is
accessible. Each mode can access
– the program counter r15 (PC)
– a particular r13 (stack pointer SP) and r14 (subroutine link register,
LR)
– a particular set of r0-r12 registers
– the current program status register (CPSR)

• Privileged modes (except System mode) can also access

– a particular SPSR (saved program status register)

Semiconductors 17
 User and
System
Register Banking
r0
r1
r2
r3
r4
Banked registers
r5
r6 FIQ IRQ Supervisor Abort Undefine
r7 d
r8 r8_fiq
r9 r9_fiq
r10 r10_fiq
r11 r11_fiq
r12 r12_fiq
r13 (SP) r13_fiq r13_irq r13_svc r13_abt r13_und
(SP) (SP) (SP) (SP) (SP)
r14 (LR) r14_fiq r14_irq r14_svc r14_abt r14_und
(LR) (LR) (LR) (LR) (LR)
r15 (PC)

CPSR SPSR_fiq SPSR_irq SPSR_svc SPSR_abt SPSR_und

Semiconductors 18
 Registers in Thumb State
• The Thumb state register set is a subset of the ARM state
set. The programmer has direct access to:
– eight general registers r0 - r7
– the program counter PC
– a Stack pointer SP
– a Link register LR
– the current program status register CPSR

• In Thumb state, the high registers (r8 - r12) are not part of
the standard register set. The assembly language
programmer has limited access to them, but can use them
for fast temporary storage
Semiconductors 19
 Thumb vs. ARM
r0 r0
r1 r1
r2 r2
Thumb r3 r3
state r4 r4

Low r5 r5
registers r6 r6
r7 r7
r8
Thumb ARM
r9

State State r10

Thumb r11
state r12
High r13 (SP) r13 (SP)
registers r14 (LR) r14 (LR)
r15 (PC) r15 (PC)

CPSR CPSR
SPSR SPSR

Semiconductors 20
 Register Overview
User and FIQ IRQ Supervis Abort Undefine
System or d
r0 r0 r0 r0 r0 r0
r1 r1 r1 r1 r1 r1
Thumb state Low

r2 r2 r2 r2 r2 r2
r3 r3 r3 r3 r3 r3
r4 r4 r4 r4 r4 r4
registers

r5 r5 r5 r5 r5 r5
r6 r6 r6 r6 r6 r6
r7 r7 r7 r7 r7 r7
r8 r8_fiq r8 r8 r8 r8
r9 r9_fiq r9 r9 r9 r9
Thumb state High

r10 r10_fiq r10 r10 r10 r10

r11 r11_fiq r11 r11 r11 r11
r12 r12_fiq r12 r12 r12 r12
registers

r13 (SP) r13_fiq r13_irq r13_svc r13_abt r13_und

(SP) (SP) (SP) (SP) (SP)
r14 (LR) r14_fiq r14_irq r14_svc r14_abt r14_und
(LR) (LR) (LR) (LR) (LR)
r15 (PC) r15 (PC) r15 (PC) r15 (PC) r15 (PC) r15 (PC)

CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_fiq SPSR_irq SPSR_svc SPSR_abt SPSR_und

Semiconductors 21
 Program Status Register (1)
31 30 29 28 27 24 23 16 15 8 7 6 5 4 0
N Z C V Q J I F T mode

Condition Reserved Control

code flags bits

• Condition Code Flags

– N: Negative or less than
– Z: Zero
– C: Carry or borrow or extend
– V: Overflow

To not corrupt reserved bits, a read-modify-write strategy should be

applied to change PSR bits.

Semiconductors 22
 Program Status Register (2)
31 30 29 28 27 24 23 16 15 8 7 6 5 4 0
N Z C V Q J I F T mode

Condition Reserved Control

code flags bits

• Interrupt Disable Bits • Mode Bits

– I: IRQ interrupts disable 10000 User
10001 FIQ
– F: FIQ interrupts disable
10010 IRQ
• T Bit 10011 Supervisor
– Thumb mode (when set) 10111 Abort
11011 Undefined
– ARM mode (when cleared)
11111 System

Semiconductors 23
 Program Counter (r15)
• When the processor is executing in ARM state
– all instructions are 32 bits wide
– all instructions must be word aligned
– bits [31:2] contain the PC, bits [1:0] are zero
(instructions cannot be halfword or byte aligned)

• When the processor is executing in Thumb state

– all instructions are 16 bits wide
– all instructions must be halfword aligned
– bits [31:1] contain the PC, bit [0] is zero
(instructions cannot be byte aligned)

Semiconductors 24
 Interrupt Handling

Semiconductors 25
 ARM Exception Vectors and processor mode

Reset Supervisor

Undefined Instruction Undefined

Software Interrupt(SWI) Supervisor

Prefetch Abort Abort

Data Abort Abort

Interrupt(IRQ) IRQ

Fast Interrupt(FIQ) FIQ

Semiconductors 26
 Exception Vectors table

.
.
.
0 FIQ
x1C
0 IRQ
x18
0 (Reserved)
x14
0 Data Abort
x10
0 Prefetch Abort
x0C
0 Software
x08
0
Interrupt
Undefined
x04
0 Instruction
Reset
x00

Semiconductors 27
 Exception Handling
• Entering an exception the ARM core
– saves the address of the next instruction in the appropriate LR
r15 (PC) r14_<mode>
(LR)

– copies the CPSR into the appropriate SPSR

CPSR SPSR_<mode>

– sets appropriate CPSR bits

• interrupt disable bits 8 7 6 5 4 0
mode
CPSR: I F T
• mode field bits
• if running in Thumb state, enter ARM state* Control
bits
– forces PC to fetch next instruction from relevant exception vector
*: all exceptions switch to ARM state!

Semiconductors 28
 Leaving Exception(1)
• To leave an exception, the exception handler must
– copy SPSR back into CPSR
SPSR_<mode> CPSR

(automatically restoring also I, F and T)

8 7 6 5 4 0

CPSR: I F T mode

Control
bits

– move contents of current LR minus offset* to PC

PC - offset
r14_<mode> r15 (PC)
(LR)

*: varies according to type of exception: 2, 4

Semiconductors 29
 Leaving Exception-Example(2)
• After servicing IRQ execute the following instruction

SUBS PC,R14_irq,#4
• This restores both PC and CPSR

SPSR_irq> CPSR

PC - offset
r14_<irq> (LR) r15 (PC)

Semiconductors 30
 Multiple Exceptions
• Exception priorities
– When multiple exceptions arise at the same time, a fixed priority
sytem determines the order in which they are handled

1. Reset highest priority

2. Data Abort (data memory access cannot be completed)
3. FIQ
4. IRQ
5. Prefetch Abort (instruction memory access cannot be
completed)
6. Undefined Instruction
7. SWI - Software Interrupt (to enter supervisor mode) lowest priority

Semiconductors 31
 FIQ-Why is it called so ?

• This mode has its own set of banked registers

from R8-R12. Hence no or minimal stack
operations are required

• FIQ is the last interrupt vector in the vector table.

Hence jump is not needed to reach ISR

• ARM recommends only one interrupt source to

be classified as FIQ

Semiconductors 32
 Interrupt Latency

• Latency could be between 5 to 27

processor clocks

• Ask customers to refer to ARM7TDMI-S

Technical Reference Manual for details

Semiconductors 33
 Instruction Pipeline

Semiconductors 34
 Instruction Pipeline

• The ARM7TDMI-S core uses a pipeline to increase the

speed of the flow of instructions to the processor. This
enables several operations to take place simultaneously
• The Program Counter (PC) points to the instruction being
fetched rather than to the instruction being executed
• During normal operation, while one instruction is being
executed, its successor is being decoded, and a third
instruction is being fetched from memory

Semiconductors 35
 3-Stage Instruction Pipeline

ARM Thum
b

PC Fetch Instruction Fetched from

Memory
PC
Thumb only: Thumb instruction
PC - Decode decompressed to ARM
4 PC - 2 instruction
Instruction decoded
Execute
PC - PC - 4 Registers read from Register
Bank, Shift and ALU operations
8 performed, Registers written
back to Register Bank

Semiconductors 36
 Optimal Pipelining
– In this example it takes 6 clock cycles to execute 6 instructions
– All operations are on registers (single cycle instructions)
– Clock cycles per instruction (CPI) = 1

ADD Fetch Decod Execut

e e
SUB Fetch Decod Execut
e e
MOV Fetch Decod Execut
e e
AND Fetch Decod Execut
e e
ORR Fetch Decod Execut
e e
EOR Fetch Decod Execut
e e
CMP Fetch Decod
e
RSB Fetch
1 2 3 4 5 6 7 8
Cycle
Semiconductors 37
 Branch Pipeline Example
– Branches break the pipeline
– Example in ARM state

BL 0x8000 Fetch Decod Execut Linkre Adjust

e e t
X 0x8004 Fetch Decod
e
X 0x8008 Fetch
ADD 0x8FEC Fetch Decod Execut
e e
SUB 0x8FF0 Fetch Decod Execut
e e
Decod
MOV 0x8FF4 Fetch
e
AND 0x8FF8 Fetch

1 2 3 4 5 6 7
Cycle
Semiconductors 38
 Reference

• ARM Architecture Reference Manual

– Available with ARM tools
– Also available on PDF

• ARM System-on-Chip Architecture

– By Steve Furber

Semiconductors 39