DELAY CALCULATION

-BY VENKATA SURENDRA AMARA (19555)

DELAY CALCULATION

CONTENTS

DELAY:
Delay, a measurement of the time for a signal to reach its destination.

In VLSI designs delays are mainly caused due to parasitics extraction.

Entire functionality may get effect due to these parasitic delays.

Delay Calculation

Pre Layout Timing

(WIRE LOAD MODEL)

Post Layout Timing

(STANDARD DELAY FILE)

Types Of Delays :
Delays are mainly classified into three types. They are..

Propagation Delay Transition Delay Slack Calculation

Timing is Based on Cell and Net Delays:

Propagation delay, a measurement of the time for a signal to reach its destination.
Propagation Delay of a cell is depends upon the input slew and load capacitance. Propagation Delay = F(slew, load capacitance) For a give gate the propagation delays are calculated using library file.

Here the delays are calculated at exactly 50% of the rise and fall time of the signal.

Propagation Delay Calculation Using Library:

pin (OUT) { max_transition : 1.0; timing() { related_pin : "INP1"; timing_sense : negative_unate; cell_rise(delay_template_3x3) { index_1 ("0.1, 0.3, 0.7"); /* Input transition */ index_2 ("0.16, 0.35, 1.43"); /* Output capacitance */ values ( /* 0.16 0.35 1.43 */ \ /* 0.1 */ "0.0513, 0.1537, 0.5280", \ /* 0.3 */ "0.1018, 0.2327, 0.6476", \ /* 0.7 */ "0.1334, 0.2973, 0.7252"); } cell_fall(delay_template_3x3) { index_1 ("0.1, 0.3, 0.7"); /* Input transition */ index_2 ("0.16, 0.35, 1.43"); /* Output capacitance */ values ( /* 0.16 0.35 1.43 */ \ /* 0.1 */ "0.0617, 0.1537, 0.5280", \ /* 0.3 */ 0.2027, 0.5676", \ /* 0.7 */ "0.1034, 0.2273, 0.6452"); }

"0.0918,

Transition Delay , a measurement of the time for a signal to change from Logic 1 to Logic 0 or Logic 0 to Logic 1.

Tfall

Trise

Transition Delay Calculation Using Library:

pin (OUT) { max_transition : 1.0; timing() { related_pin : "INP1"; timing_sense : negative_unate; Rise_transition(delay_template_3x3) { index_1 ("0.1, 0.3, 0.7"); /* Input transition */ index_2 ("0.16, 0.35, 1.43"); /* Output capacitance */ values ( /* 0.16 0.35 1.43 */ \ /* 0.1 */ "0.0513, 0.1537, 0.5280", \ /* 0.3 */ "0.1018, 0.2327, 0.6476", \ /* 0.7 */ "0.1334, 0.2973, 0.7252"); } Fall_transition(delay_template_3x3) { index_1 ("0.1, 0.3, 0.7"); /* Input transition */ index_2 ("0.16, 0.35, 1.43"); /* Output capacitance */ values ( /* 0.16 0.35 1.43 */ \ /* 0.1 */ "0.0617, 0.1537, 0.5280", \ /* 0.3 */ 0.2027, 0.5676", \ /* 0.7 */ "0.1034, 0.2273, 0.6452"); }

"0.0918,

Delay Calculation Basics:

A typical design comprises of various combinational and sequential cells.

Every net in the design has a capacitive load which is the sum of the pin capacitance loads of every fanout of the net plus any contribution from the interconnect.

Logic Block Representation Depicting Capacitances:

Without considering the interconnect parasitics, the internal net NET0 has a net capacitance which is comprised of the input pin capacitances

Inputs I1 and I2 have pin capacitances corresponding to the UAND1 and UINV0 cells.
The output O1 has the pin capacitance of the UNOR2 cell plus any capacitive loading for the output of the logic block.

Cell Delay using Effective Capacitance:

The effective capacitance approach attempts to find a single capacitance that can be utilized as the equivalent load so that the original design as well the design with equivalent capacitance load behave similarly in terms of timing at the output of the cell.

Ceff= C1+k*C2, 0<=k<=1

Waveform at the output of the cell with various loads:

The effective capacitance is a function of: 1.The driving cell, and 2.The characteristics of the load or specifically the input impedance of the load as seen from the driving cell

Interconnect Delay
Interconnect parasitics of a net are normally represented by an RC circuit RC interconnect can be pre-layout or post-layout Using the effective capacitance approach, the delay through the driving cell and through the interconnect are obtained separately For pre-layout analysis, the RC interconnect structure is determined by the tree type, which in turn determines the net delay.

Pre Layout Timing

Wireload Models:
Prior to floorplanning or layout, wireload models can be used to estimate capacitance, resistance and the area overhead due to interconnect. The wireload model is used to estimate the length of a net based upon the number of its fanouts. Average net length increases as the block size is increased. For different areas (chip or block size), different wireload models would typically be used in determining the parasitics. Resistance is resistance per unit length of the interconnect, capacitance is capacitance per unit length of the interconnect, and area is area overhead per unit length of the interconnect.

Wireload model cond..

Here is an example of a wireload model. wire_load ("wlm_conservative") { resistance : 5.0; capacitance : 1.1; area : 0.05; slope : 0.5; fanout_length (1, 2.6); fanout_length (2, 2.9); fanout_length (3, 3.2); fanout_length (4, 3.6); fanout_length (5, 4.1); }

Length = 4.1 + (8 - 5) * 0.5 = 5.6 units Capacitance = Length * cap_coeff(1.1) = 6.16 units Resistance = Length * res_coeff(5.0) = 28.0 units Area overhead due to interconnect = Length * area_coeff(0.05) = 0.28 area units Here Delay Tnet = RC = 6.16 * 28.0 = 72.8 ns

Post-layout Timing :
The parasitics of the metal traces map into an RC network between driver and destination cells.

Output load of the inverter cell UINV0 is comprised of an RC structure. Resistive load at the output pin implies that the NLDM tables are not directly applicable.

Elmore Delay
Elmore delays are applicable for RC trees. What is an RC tree? An RC tree meets the following three conditions: Has a single input (source) node. Does not have any resistive loops. All capacitances are between a node and ground. Elmore delay can be considered as finding the delay through each segment, as the R times the downstream capacitance, and then taking the sum of the delays from the root to the sink. Elmore delay is mathematically identical to considering the first moment of the impulse response

Elmore Delay Cond..

The delays to various intermediate nodes are represented as:

Elmore Delay Cond.. The equivalent RC network can be simplified as a PI network model or a T-representation. Based upon Elmore delay equation: Net Delay = Rwire * (Cwire / 2 + Cload)

Balanced tree model: Net Delay = (Rwire / N) * (Cwire / (2 * N) + Cpin) Worst-Case Tree Model : Net delay = Rwire * (Cwire / 2 + Cpins)
(Cpins is the total pin load from all fanouts,N-FanOut)

Elmore Delay Cond..

Worst-Case Tree Model: Net delay = Rwire * (Cwire /2 + Cpins) = 0.3 * (0.5 + 2.3) = 0.84 Balanced Tree Model: Net delay to NOR2 input pin = (0.3/2) * (0.5/2 + 1.3) = 0.2325 Net delay to BUF input pin = (0.3/2) * (0.5/2 + 1.0) = 0.1875

Asymptotic Waveform Evaluator AWE Model

By considering the higher order estimates, greater accuracy for computing the interconnect delays is obtained. But it takes longer time to calculate than ELMORE DELAY.

Slew Merging
Input transition of a cell is known as slew. When multiple slews arrive at a common point, such as in the case of a multi-input cell or a multi-driven net? Such a common point is referred to as a slew merge point.

Path delay

Which slew is chosen to propagate for- ward at the slew merge point?

Max Path Analysis:

Worst slew propagation: A->Z is exact path and it is pessimistic for B->Z. Worst arrival propagation: B->Z is exact path and it is optimistic for A->Z.

Min Path Analysis:

Best slew propagation: B->Z is exact path and A->Z is pessimistic for min path analysis.
Best arrival propagation: A->Z is exact path and B->z is optimistic for min path analysis.

Slew Thresholds
In general, a library specifies the slew (transition time) threshold values used during characterization of the cells. The question is, what happens when a cell with one set of slew thresholds drives other cells with different set of slew threshold settings? Let us consider the slew settings for cell U1 in the cell library as: slew_lower_threshold_pct_rise : 20.00 slew_upper_threshold_pct_rise : 80.00 The cell U2 from another library can have the slew settings: slew_lower_threshold_pct_rise : 10.00 slew_upper_threshold_pct_rise : 90.00 The cell U3 from yet another library can have the slew settings : slew_lower_threshold_pct_rise : 30.00 slew_upper_threshold_pct_rise : 70.00

Post Layout Timing:

Pre Layout Timing:

For Pre Layout Design, the relationship between the 10-90 slew and the 20-80 slew is given by:

Here interconnect resistance is not consider.

slew2080 / (0.8 - 0.2) = slew1090 /(0.9 - 0.1) Thus, a slew of 500ps with 10-90 measurement points corresponds to a slew of (500ps * 0.6) / 0.8 = 375ps with 20-80 measurement points. Similarly, a slew of 600ps with 20-80 measurement points corresponds to a slew of (600ps * 0.8) / 0.6 = 800ps with 10-90 measurement points.

Voltage Domains
A typical design may use different power supply levels for different portions of the chip. Level shifting cells are used at the interface between different power supply domains.

Notice that the delay is calculated from the 50% threshold points

Path Delay Calculation :

For a selected path adding up all net and cell timing arcs gives the total path delay. Combinational Path Delay:

Tfall = Tn0rise + Tafall + Tn1fall + Tbrise + Tn2rise + Tcfall + Tn3fall Trise = Tn0fall + Tarise + Tn1rise + Tbfall + Tn2fall + Tcrise + Tn3rise

Input to Flip-flop Path:

Trise = Tn1rise + Tafall + Tn2fall + Tbuf1fall + Tn3fall + Tbrise + Tn4rise Tfall = Tn1fall + Tarise + Tn2rise + Tbuf1rise + Tn3rise + Tbfall + Tn4fall The capture clock path delay for a rising edge on input MCLK is: Tn5rise + Tbuf2rise + Tn6rise

Flip-flop to Flip-flop Path:

Trise = Tck2qrise + Tn1rise + Tafall + Tn2fall + Tbfall + Tn3fall

The launch clock path delay for a rising edge on input PCLK is: Tn4rise + T5rise + Tn5arise
The capture clock path delay for a rising edge on input PCLK is: Tn4rise + T5rise + Tn5brise + T6rise + Tn6rise

Multiple Paths:
The longest path is the one that takes the longest time; this is also called the worst path, a late path or a max path. The shortest path is the one that takes the shortest time; this is also called the best path, an early path or a min path. The longest path between the two flip-flops is through the cells UBUF1, UNOR2, and UNAND3. The shortest path between the two flip-flops is through the cell UNAND3.

Slack Calculation
Slack is the difference between the required time and the time that a signal arrives.
SLACK = REQUIRED ARRAIVAL TIME ACTUAL ARRAIVAL TYM

SLACK = RAT (Tclk2q+Tcomb+Tnet)

Ts Th

DATA ARRIVES

Ts Th

Tclk2q

Tcomb

Tnet

SLACK

0
DATA

RAT AAT

10

20