Synthesis

Automatic method of converting a higher level of abstraction to a lower level of abstraction RTL to gate level netlist and it consist of interconnected gate level micro cells Gate level cells contained in technology libraries for each type of technology supported

Synthesis
Net lists optimized for area, speed and testability and so on Synthesis process:

Synthesis
Inputs to the synthesis process are; RTL VHDL description, circuit constraints and technology library It produce an optimized netlist

Register Transfer Level Description

Style specifies all of registers in a design and combinational logic between Register and cloud diagram:

Registers are described by component instantiation Combinational logics by equations, sequential statements, subprograms, concurrent statements, etc
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RTL
Eg:

RTL
Schematic representation

RTL
The circuit can also described by register inference

RTL
First model uses component instantiation and the second model uses register inferences Both uses RTL description, but second one is technology independent Designer must know the details of technology libraries that contains components After synthesis both will produce the gate level description

RTL
Gate level description

Two registers and one multiplexer Depends on technology library

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 Typical netlist generated

RTL

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Constraints
To control the output of the optimization and mapping process Provide a control over structural implementation of the design It includes area, timing, power, testability, packaging, layout, etc.

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Constraints
Possible constraints in the Register and Cloud diagram

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Constraints
Clouds represents combinational logic, interconnection wires etc The constraints are:
1. Timing constraints 2. Late arrival constraints 3. Clock cycle constraints

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Timing constraints
Specify maximum delay for particular path in a design Guides optimization and mapping to produce a netlist that meet the timing constraint One of the most difficult task when designing ASIC or FPGA using synthesis tools Typical format (Leonardo synthesis format) Maximum delay for signal data_out should be greater than or equal to 25 library units One library unit may be ns or ps, can be set by the designer
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Clock constraints
Time constraints to every flip flop input with a value of clock cycle To meet optimized clock cycle An eg: Sets a clock cycle constraint on port clk with a value of 25 library units

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Attributes
To specify the design environment Specify loading, driving, timing of signals in the design All information is taken into a static timing analyzer to calculate the timing through the circuit paths

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Attributes
Cloud diagram with attributes:

Load:
Each input can have a load value specified that determines how much it will slow a particular driver
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Attributes
Load attribute specifies how much capacitive load exists on a particular output signal The unit of the load value is in terms of pF or standard loads or so on. For a weak driver or a large capacitive load, timing analyzer calculates a long delay, otherwise short delay An eg: The signal xbus will load a driver of this signal with 5 library units of a load
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Attributes
Drive:
Specifies the resistance of the driver, which control how much current it can source Specifies the units of the technology library Larger driver is faster, but require more area, so there is a compromise between these two An eg: The signal ybus has 2.7 library units of driver capability
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Attributes
Arrival time: Suitable for late arrival signals The path for such inputs are faster then any other input path

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Technology Libraries
Hold information necessary for a synthesis tool to create netlist for a design based on the desired logic behavior and constraints on the design All information to correct choices to build a design Contains logic function of ASIC cell, area of the cell, input to output timing of the cell, constraints on fan out of the cell, the timing check that are required for the cell, and graphical symbol of the cell for the use in schematics

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Technology Libraries
An eg: A 2-input AND gate written in Synopsys.lib format:

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Technology Libraries
Synthesis tool have complicated delay models to calculate timing through an ASIC cell Delay models include:
1. 2. 3. 4. Intrinsic rise time and fall time Output loading delay Input slope delay Wire delay

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Technology libraries
An eg:

Total delay from gate A1 to C1 is

Intrinsic delay: Delay of the gate without any loading Loading delay: Delay due to the input capacitance of the gate being driven Wire delay: Delay due to the interconnection wires (depends on size of the chip die) Slope delay: Delay due to heavily loading or light drive
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Technology Libraries
Also contain data about how to scale delay information with respect to process parameters and operation conditions like temperature, power supply, etc.

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Synthesis
Three steps are required to translate RTL to gates:
1. Translate RTL to unoptimized boolean description (only primitive gates AND and OR gates, FFs and latches) 2. Perform boolean optimization algorithms 3. Mapping optimized boolean description to actual logic gates
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Translation
Translation from RTL description to boolean equivalent description is not user controllable An intermediate form is generated in a format that is optimized for a particular tool and is not viewable by the user All IF, CASE and LOOP statements, conditional statements and selected signal assignment statements are converted to their boolean equivalent in its intermediate form FFs and latches produce the same FF or latch entry in the intermediate description

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Boolean Optimization
Unoptimized boolean description is converted to an optimized boolean description Number of algorithms and rules are there PLA optimization technique:
Convert unoptimized boolean description to a very low-level description (pla format) Optimize that low-level description and reduce the logic generated by sharing common terms

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Flattening
Process of converting unoptimized boolean expression to a pla format Creates a flat signal of only two levels: an AND level and an OR level PLA structure is very easy description, since simple structure and algorithm

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 An eg:

Flattening

Flattening remove intermediate variables

The resultant design is usually very fast But slower than one that has more logic level due to fanout loading on the input signals Another problem is the design is large, since no sharing between terms An N-input XOR has 2^(N-1) terms, such functions cannot be flattened
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Factoring (Structuring)
Process to add intermediate terms to add structure to a description Opposite to flattening An eg: Before factoring After factoring

Better design, but design dependent Smaller design, but slower design
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Mapping to gates
Takes optimized boolean description to netlist using timing and logical information from technology library Netlist is targeted to users need for area and speed Faster netlist require lot of library cells to implement, others take small numbers, but very slow

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Mapping to gates
An eg: VHDL description of 8-bit adder

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Smaller and slower design

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Bigger and faster design

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