JTAG AN IEEE 1149.

1 STD

OVERVIEW
In today's complex systems, testability is an increasing concern in almost every application and in every area of application development. Manufacturers that thoroughly address the issue of testability at the device, board, and system levels deliver more consistently reliable and cost-effective products to the marketplace. This means building in test capabilities in every phase of development and deployment, including design verification, hardware and software integration, manufacturing, and in the field.

JTAG HISTORY
In the 1980s, the Joint Test-Action Group (JTAG) formed by representatives from makers and users of components and boards, recognized that only a cooperative effort could address the mounting testability problems in a coordinated way. Its mandate was to propose design structures that semiconductor makers would incorporate into device designs to aid in testing boards and systems. In 1990 the IEEE adopted the proposal as IEEE Standard 1149.1-1990- BOUNDARY SCAN. Its stated purpose was to test interconnections between Integrated Circuits (ICs) installed on boards, modules, hybrids, and other substrates. Manufacturers adopting the standard could also test the IC itself . In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications, corrections, and enhancements. In 1994, a supplement containing a description of the Boundary-Scan Description Language (BSDL) was added to the standard. Since that time, this standard has been adopted by major electronics companies all over the world.

 Applications are found in high volume, high-end consumer products, telecommunication products, defense systems, computers, peripherals, and avionics. In fact, due to its economic advantages, some smaller companies that cannot afford expensive in-circuit testers are using boundary-scan. The boundary-scan test architecture provides a means to test interconnects between integrated circuits on a board without using physical test probes.

What is boundary-scan?
Boundary-scan, as defined by the IEEE Std.-1149.1 standard, is an integrated method for testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated circuit (IC) level. The inability to test highly complex and dense printed circuit boards using traditional in-circuit testers and bed of nail fixtures was already evident in the mid eighties. Due to physical space constraints and loss of physical access to fine pitch components and BGA devices, fixturing cost increased dramatically while fixture reliability decreased at the same time.

DIGITAL BOUNDARY SCAN (IEEE Std. 1149.1)

Basic Concept
Standard 1149.1 defines a test access protocol and a boundary-scan architecture for digital integrated circuits and the digital portions of mixed analog/digital integrated circuits. the name boundary scan is due to the insertion of a boundary-scan cell to each I/O pin of the original circuit and the chaining of these cells into a shift Register called the boundary-scan register. Chips complying with this standard can be readily integrated into a PCB with their I/O accessible through the boundary-scan registers.

JTAG ARCHITECTURE
Architecture IEEE Standard 1149.1 is a testing standard. However it is described as a collection of design rules applied principally at the IC level that allow software to alleviate the growing cost of designing and producing digital systems. The primary benefit of the standard is its ability to transform extremely difficult printed circuit board testing problems that could be attacked with ad-hoc testing methods into well-structured problems that software can easily and swiftly deal with.

BOUNDARY SCAN HARDWARE

The boundary-scan circuitry can be divided into four main hardware components: A test access port (TAP), which consists of four mandatory terminalstest data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK)and one optional terminal, test reset (TRST) A TAP controller (TAPC) An instruction register (IR) and its associated decoder Several test data registers, including the mandatory boundary-scan register and bypass register, and some optional miscellaneous registers, such as the device-ID register, and some design-specific test data registers.

BOUNDARY SCAN ARCHITECTURE

The test access port, which defines the bus protocol of the boundary scan, consists of additional I/O pins necessary for each chip employing the standard. The TAP controller is a 16-state, finite-state machine that controls each step of the boundary-scan operations. Each instruction to be carried out by the boundaryscan architecture must be serially loaded into the instruction register through the test data input (TDI) pin. The test signals to configure the boundary-scan-related test hardware for the current test instruction are provided by the associated decoder. The test data registers are used to store test data or some system-related information (such as the chip ID, company name, etc.). (such as the chip ID, company name, etc.). In addition to the hardware components, IEEE Std. 1149.1 also defines a set of test instructions, including four mandatory ones (BYPASS, SAMPLE, PRELOAD, and EXTEST) and several optional ones, including INTEST, RUNBIST, CLAMP, IDCODE, USERCODE, and HIGHZ. It also allows the users to define their own instructions.

TYPICAL TEST PROCEDURE

A boundary-scan test instruction is shifted into the IR through the TDI. The instruction is decoded by the decoder associated with the IR to generate the required control signals so as to properly configure the test logic. A test pattern is shifted into the selected data register through the TDI and then applied to the logic to be tested. The test response is captured into some data register.

 The captured response is shifted out through the TDO for observation and, at the same time, a new test pattern can be scanned in through the TDI. Steps 3 to 5 are repeated until all test patterns are shifted in and applied, and all test responses are shifted out.

Test Access Port and Bus Protocols

Test clock input
(TCK) is a clock input to synchronize the test operations between the various parts of a chip or between different chips on a PCB. This input must be independent of the system clocks so the serial test data path between components of a chip or different chips can be used independently of the system clocks, which may vary significantly in frequency from one component to another; so the board interconnect testing can be properly carried out; and so the shifting and capturing of test data can be executed concurrently with normal system operation, thereby facilitating online system monitoring for a design without changing the state of the on-chip system logic.

 Test data input is an input to allow test instructions and test data to be serially loaded into the instruction register and the various test data registers, respectively. Values presented at TDI are clocked into the selected register on a rising edge of TCK.

 Test data output TDO) is an output to allow various test data to be driven out. changes in the state of the signal driven through TDO should occur only on the falling edge of TCK.

 Test mode select (TMS) is the sole test control input to the TAP controller. All boundary-scan test operations such as shifting, capturing, and updating of test data are controlled by the test sequence applied to this input. Signals presented at TMS are sampled by the TAP controller on the rising edge of TCK. This input should also be driven to logic 1 when it is inactivated.

 Test reset (TRST) is an optional pin used to reset the TAP controller. TRST pin is implemented, the TAP controller can be asynchronously reset to the TestlogicReset controller state when a logic 0 is applied at TRST. This in turn will reset other boundary-scan logic to the state required by the TestLogicReset state. This pin should not be used to reset the system logic so the test logic can be reset independently of the on-chip system logic. If this input is omitted, the system must have some circuitry that can reset the TAP controller during power-on.

BOUNDARY-SCAN REGISTER (BSR)

TAP Controller
The TAP controller (TAPC) is a 16-state, finite-state machine added on the IC die itself. It recognizes the communication protocol and generates internal control signals used by the remainder of the Boundary Scan logic. It recognizes the communication protocol and generates internal control signals used by the remainder of the Boundary Scan logic. The TAP controller is driven by TCK and TMS only; no other signals affect TAP controller. They program the TAP Controller as a 16-state machine, generating clock and control signals for the instruction and data registers.

Only two events can trigger a change of controller state: a test-clock rising edge, system power-up. Movement through the state machine is controlled by the value of TMS, a set-up time prior to the rising edge of TCK. The 1s and 0s adjacent to each state transition arc show the value that must be present on TMS at the time of the next rising edge of TCK

 The main functions of the TAPC include:

Resetting the boundary-scan architecture Providing control signals to load instructions into the instruction register Providing signals to perform test functions such as Capture and Update (application) of test data Providing control signals to shift test data from TDI to TDO

 The 16 states can be divided into three parts. The first part (the 2 states at left)
contains the reset and the Run-Test/Idle states, the second (the 7 states in the middle) and third (the 7 states at right) parts control the operations of the data and instruction registers, respectively.

JTAG TAP State definitions

Test-Logic-Reset
For a target device in the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their power-up values.

Whenever a 0 signal is applied to the TRST port, the TAPC enters this state. The TAPC can also be synchronously reset; whatever state the TAP controller is in, it will return to this state if a logic 1 is applied to TMS for five consecutive TCK cycles (i.e., five rising edges of TCK).

Run-Test/Idle
For a target device, Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle.

Select-DR-Scan, Select-lR-Scan
For a target device, no specific function is performed in the Select-DR-Scan and SelectlR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either dataregister scan or instruction-register scan.

Capture-DR
For a target device in the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the Capture-DR state is exited.

Shift-DR
For a target device, upon entry to the Shift-DR state, the selected data register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO outputs the logic level present in the least-significant bit of the selected data register. While in the stable Shift-DR state, data is shifted serially through the selected data register on each TCK cycle.

Exit1-DR, Exit2-DR
For a target device, the Exit1-DR and Exit2-DR states are temporary states that end a dataregister scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the highimpedance state.

Pause-DR
For a target device, no specific function is performed in the stable Pause-DR state. The Pause-DR state suspends and resumes dataregister scan operations without loss of data.

Update-DR
For a target device, if the current instruction calls for the selected data register to be updated with current data, such update occurs on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR
For a target device in the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the Capture-IR state is exited.

Shift-IR
For a target device, upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO outputs the logic level present in the leastsignificant bit of the instruction register. While in the stable Shift-IR state, instruction data is shifted serially through the instruction register on each TCK cycle.

Exit1-IR, Exit2-IR
For a target device, the Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR
For a target device, no specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data.

Update-IR
For a target device, the current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state.