8255 PPI

A device used to implement data transfer between processor and peripherals like ADC, DAC, keyboard, 7 segment display Has three 8 bit ports- Port A, Port B, Port C Has three operating modes Mode 0 - Simple I/O Mode 1 Handshake I/O Mode 2-Bidirectional I/O

8255 PPI

8255 PPI
A - can be programmed as input or output port. It can also be an 8-bit bidirectional port. B - also can be programmed as in input or output port. It cannot be used as an 8-bit bidirectional port. C - can also be either an input or an output port. Can be split into two 4 bit ports. Each 4 bit port can be either an input or an output port. Also, bits of C port can be set/reset individually through program.

Modes of operation of 8255

Mode 0 All three ports can be programmed as either input or output port. Outputs are latched and inputs are not latched. This mode can be used to interface DIP switches, LEDs, hex keypad, 7 segment display

Modes of operation of 8255

Mode 1 Here only Port A and B can be programmed as input/output port. Handshake signals are exchanged between processor and peripheral. Port C provides the hand shake signals. Input and output data are latched. Interrupt driven data transfer scheme possible

Modes of operation of 8255

Mode 2 Port A can be programmed as bidirectional port. Five pins of Port C provide the handshake signals. Port B can be in mode 0 or mode 1 Used in applications such as data transfer between computers or floppy disk controller interface

Addressing ports of 8255

CS 0 0 0 0 1 A0 0 0 1 1 x A1 0 1 0 1 x Port Selection Port A Port B Port C Control register 8255 not selected

Has two control words I/O Mode Set Control Word(MSW) Bit Set Reset Mode (BSR)

Control Word- I/O Mode

Control Word-BSR Mode

Mode 1 of 8255 (Port A - Input Port)

Mode 1 of 8255 (Port A - Input Port)

If IBFA signal is low input device place data on PA0-PA7 STBA is asserted low and data is latched at port and IBFA is set to high INTRA is set high and processor is interrupted through NMI RD is asserted low and data is read from port A, IBFA is set to low and the input device can send the next data For Port B as input port handshake signals provided by PC0,PC1,PC2 are used.

Mode 1 of 8255 (Port A - Output Port)

Mode 1 of 8255 (Port A - Output Port)

WR is asserted low and processor writes to output port OBFA is asserted low indicating that output buffer is full. The output device accepts the data and sends the acknowledgement by asserting ACKA low. The processor is interrupted through INTRA signal given through NMI For Port B as output port handshake signals provided by PC0,PC1,PC2.

Mode 2 of 8255

Interfacing of 8255 with 8086

DMA Data Transfer Scheme

Normal data transfer between memory and I/O device take place through processor. DMA enables data transfer directly between I/O and memory. This will allow large amount of data transfer in a short time. For this a dedicated hardware called DMA Controller is used. DMA controller temporarily borrows the system bus from the processor and transfer the data bytes directly.

Block diagram DMA Controller

DMA Transfer
Has a number of channels and each channel can may service an I/O independently Each channel has a address register, control register and count register. DMA controller works as master or slave In slave mode the processor loads the address register with starting address, count register with no of bytes and control register with control information.

DMA Transfer
I/O needs DMA transfer First DMA request signal is sent to DMA controller DMA controller sends hold request to processor At the end of current instruction processor release the control of buses. Processor sends hold acknowledgement DMA controller takes control of system bus (starts master mode)

DMA Transfer
DMA controller sends DMA acknowledgement With this the device is ready for data transfer DMA Read Operation Controller output the memory address on address bus Asserts memory read and IO write signals Memory output the data on data bus and this is written to IO port

DMA Transfer
DMA write operation DMA controller output the memory address and asserts memory write and IO read signals IO device output data on data bus and is written to memory After data transfer the processor takes control of buses DMA can be as bytes of data or blocks of data.

DMA Transfer

Cycle stealing DMA-byte data transfer in between instruction cycles.

Burst Mode DMA- Blocks of data are transferred

Internal Architecture of 8257

Features of 8257 DMA Controller

It has four DMA channels to service 4 I/O devices. Each channel can be independently programmed to transfer upto 64kbytes of data by DMA. Each channel has two programmable registers- One to program the starting address of memory location for DMA data transfer. Another to program a 14 bit count value and a 2 bit code for type of DMA (read/write/verify).

Features of 8257 DMA Controller

Read Transfer-Data is transferred from memory to I/O device. Write Transfer- Data is transferred from I/O device to memory. Verification-generates the DMA addresses without DMA memory and I/O signals. Mode set register-Used to program various features of 8257 Status register-can be read to know the terminal count status of the channels.

Features of 8257 DMA Controller

Registers are addressed during slave mode through A3-A0 lines. Channel 0 DMA add. reg. 0000 Channel 0 Count reg. 0001 Channel 1 DMA add. Reg. 0010 Channel 1 Count reg. 0011 Channel 2 DMA add. Reg. 0100 Channel 2 DMA Count reg. 0 1 0 1 Channel 3 DMA add. Reg. 0110 Channel 3 Count reg. 0111 Mode(wr. )/Status (rd.) 1000

Count register of 8257

Mode Set Register

Status Register

DMA operation in 8086 using 8257

Slave Mode- Control word is send to mode register, program count and address registers of the required DMA channels. 8257 will keep on checking for DMA request from peripherals. DMA sequence of operations are as follows Peripheral will assert DRQ signal high A channel is enabled and 8257 will assert HRQ high

DMA operation in 8086 using 8257

8086 will complete the current instruction execution, drive all its buses to high impedance state and asserts HLDA signal 8257 on receiving acknowledgement from 8086 will send DACK. 8257 asserts AEN high which enable DMA memory address latches and disable processor address latches. 8257 outputs the DMA address ADSTB is asserted to latch the address in external latches.

DMA operation in 8086 using 8257

Once address is output on address lines the content of address register is incremented by one and count register is decremented by one. 8257 asserts appropriate read and write signals to perform DMA transfer between peripheral and memory. After performing one byte transfer the steps of loading address and DMA transfer is repeated till TC.

Interfacing 8086 with 8257

8259 Programmable Interrupt Controller

Manage 8 interrupts according to instructions written to its control register. Vector an interrupt anywhere in the memory map Resolve 8 levels of interrupt priorities in a variety of modes such as fully nested mode, automatic rotation mode, specific rotation mode. Mask each interrupt individually.

8259 Programmable Interrupt Controller

Be set up to accept either the level triggered or edge triggered interrupt request. Read the status of In service Interrupt, pending interrupts and masked interrupts. Can be expanded to 64 priority levels by cascading additional 8259s. Can be interfaced with 8085 and 8086.

Internal Architecture of 8259

Interrupt Handling of 8259

IRR stores requests Priority resolver checks 3 registers. IRR for requests, IMR for masking bits and ISR for interrupt being serviced. It then resolves priority and set the appropriate INT high. Processor acknowledge the interrupt through INTA. With INTA the appropriate bit is set in ISR and the corresponding bit in IRR is reset. Opcode for CALL is placed on data bus

Interrupt Handling of 8259

Program sequence is transferred to memory location specified by CALL instruction. Interrupt can be accepted in edge triggered mode or level triggered mode according to initialization instruction. Status of IRR, ISR and IMR can be read which will make the interrupt process versatile.

Programming 8259
Requires two types of command words Initialization Command Word(ICW) Operational Command Word(OCW) Initialized with 4 ICWs-2 are essential and other 2 are optional based on modes. The words should be issued in a sequence 8259 can be made to operate in various modes by 3 OCWs

ICW1

ICW2
Interrupt type MSB 5 bits and LSB 3 bits are 0 IR0

ICW3 Master Device

ICW3 Slave Device

This gives the slave identification number

ICW4

Operating Modes of 8259

Fully Nested Mode Default mode of operation IR0 has highest priority and IR7 lowest. Corresponding ISR bit is set till EOI is received. Lower priority interrupts are inhibited and higher priorities are allowed.

Operating Modes of 8259

End of Interrupt ISR is reset with AEOI of ICW4 or by EOI 2 types of EOI-specific and non specific Non specific EOI-Automatically reset highest ISR bit (fully nested mode) Specific EOI-This is to reset a particular ISR bit.

Operating Modes of 8259

Automatic Rotation IR level receives lowest priority after it is served. Next device to be served gets highest priority. Automatic EOI 8259 performs a automatic non specific EOI(ICW4)

Operating Modes of 8259

Specific Rotation Bottom priority can be selected through OCW2. If IR6 has bottom priority, IR5 next priority and IR7 highest priority. Priorities can be changed by setting rotate on specific EOI in OCW2 Special Mask Mode When a mask bit is set in OCW1 , further interrupts are masked at that level and enables interrupts from other levels

Operating Modes of 8259

Poll Command 8259 is polled by using software execution by microprocessor instead of requests on INT input. Set through OCW3. Special Fully Nested Mode Used in cascading mode to program priority in master using ICW4. Master interrupts the CPU only when the interrupting device has a higher priority than the one currently being serviced

Operating Modes of 8259

Buffered Mode In cascaded mode buffer is enabled through SP/EN pin. Cascade Mode One master and eight slaves Master control the slaves through CAS0-CAS3 which acts as chip select for slaves Slave INT outputs connected to master IR inputs. Each 8259 must be separately initialized EOI must be issued twice

OCW1
OCW1 must be sent to an 8259 to unmask any IR inputs.

OCW2
OCW2 is mainly used to reset a bit in ISR. Once ISR bit is reset 8259 can respond to interrupt signals of lower priority.

OCW2
Non Specific EOI- Terminate current interrupt being serviced by 8259. Reset the corresponding bit in ISR of 8259 and allow higher priority interrupt. Specific EOI-Terminate specific interrupt request decided by lower 3 bits of OCW2. Rotate on NEOI- rotate priority Rotate on Automatic EOI- Select AEOI with rotate priority Rotate on specific EOI-same as 2 with rotate priority.

OCW3

Interfacing of 8259 with 8086

8253 Programmable Timer

Time based activities of the processor can be performed in 2 ways: Execute a delay subroutine, Use a programmable timer Applications of programmable timer Interrupt a time sharing OS at specified intervals of time Send periodic timing signals to IO devices Baud rate generator-clock divider Measure the time between external events Used to initiate an activity through interrupt after a programmed no of external events

Internal Architecture of 8253

D7-D0 Data Bus Buffer Read/Write logic I n t e r n a l Counter 1 Clk 0 Gate 0 Out 0

RD WR A0 A1

Counter 2

Clk 1 Gate 1 Out 1

Control Word register

B u s Counter 3 Clk 2 Gate 2 Out 2

Internal Architecture of 8253

Has 3 independent programmable16 bit counters and 6 modes of operation. Each counter has clock input, gate input and counter output. For operation a count has to be loaded in count register, gate should be tied high and a clock signal is applied to clock input. Counter counts by decrementing the count value by one in each cycle of clock signal and generates an output depending on mode of operation

Internal Architecture of 8253

8254 has 8 data lines for communication with processor Address lines A0 and A1 are used to select any one of four internal device. A0 A1 0 0 Counter 0 0 1 Counter 1 1 0 Counter 2 1 1 Control register

Operating Modes of 8254

There are 6 modes of operation for 8254 Mode 0 Interrupt on TC Mode 1 Hardware retriggerable one shot Mode 2 Rate generator Mode 3 Square wave mode Mode 4 Software triggered strobe Mode 5 Hardware triggered strobe Initialization procedure for each mode Write a control word into control register Write a count value in count register

Mode 0
Count value is loaded in count register. If the gate is high the counter is decremented and provide a high output when the count is zero. Low to high transition of counter used as an interrupt to the processor to initiate any activity. Count N loaded in count register, output high after N+1 clock pulses

Mode 1
Works as a retriggerable monostable multivibrator. Gate acts as trigger pulse to start the count process (low to high transition). When count value is loaded into counter the output is low Output becomes high when count value is zero. Mode 1 produces a logic low pulse whose width is equal to the duration of count.

Mode 2
Used to generate a periodic low pulse of width equal to one clock period. A count value of N loaded in count register the output will go low once in N clock period. Gate should remain high. Counter is reloaded at the end and the pulses are repeated.

Mode 3
Counter generates a square wave. If a even number N is loaded in count register, output will be High for N/2 clock period and low for the next N/2 clock periods. If a odd number N is loaded in count register, output will be High for (N+1)/2 clock period and low for the next (N-1) /2 clock periods. Original count is reloaded and process repeated. Gate is high

Mode 4
Used to generate a single low pulse after a delay. A count N is loaded in the counter a low pulse of width equal to one clock period is generated in the (N+1)th clock period. Used as a strobe signal in parallel data transfer. Gate is high

Mode 5
Same as Mode 4 except that there should be a low to high transition at Gate. If gate makes a low to high transition before the end of count the original count value is reloaded in the next clock period.

Control Word of 8253

SC1 SC2 RW1 RW0 M2 M1 M0 BCD

SC1 SC2 0 0- Select Counter 0 01- Select Counter 1 10- Select Counter 2 1 1- illegal

RW1 RW0 M2 M1 M0 0 0- Counter latch 0 0 0 Mode 0 0 1- read/Write LSB only 0 0 1 Mode 1 1 0-Read/Write MSB only x 1 0 Mode 2 1 1- Read/Write LSB first x 1 1 Mode 3 and then MSB 1 0 0 Mode 4 1 0 1 Mode 5

BCD 1-BCD count 0-Binary count

Interfacing of 8253 with 8086

8251 Programmable Communication Interface (USART)

A programmable chip designed for synchronous and asynchronous serial data communication. There are 3 modes of serial data transmission Simplex Duplex Half Duplex

Serial Data Transmission

Simplex-Data transmitted only in one direction. Duplex-Data may transmitted in both directions simultaneously. Half Duplex-Data may be transmitted in both directions but at a time in only one direction

Serial Data Transmission

Serial data transmission can be in synchronous mode or asynchronous mode Synchronous Mode Receiver and Transmitter are synchronized. Data is sent in blocks at a constant rate The start and end of the blocks are specified with specific patterns.

Serial Data Transmission

Asynchronous Mode- Receiver and Transmitter are not synchronized. Each data character has a bit which identifies its start and stop characters. When no data is sent, line is high - mark state. Beginning of data character is indicated by the line going low for 1 bit time - start bit. Data is sent which may be 5,6,7 or 8 bits Parity bits are then sent to check error Signal line goes high for 1,11/2 ,2bits-Stop bits

Internal Architecture of 8251

D7-D0 Data Bus Buffer Read/Write Control logic I n t e r n a l Transmit Buffer Tx D

RD WR Reset Clk C/D CS DSR DTR CTS RTS

Transmit Control

Tx RDY Tx E Tx C

Modem Control register

B u s

Receive Buffer
Receive Control

RxD

Rx RDY Rx C Syndet/BD

8251 Pin Functions

D7-D0-Data bus C/D-Control or Data is to be written or read RD-Read data command WR-Write data command CS-Chip Select CLK-Clock Pulse RESET-Reset TxC-Transmitter clock RxC-Receiver clock

8251 Pin Functions

RxD-Receive Data RxRDY-Receiver Ready(has character for CPU) TxRDY-Transmitter ready (ready for character from CPU) DSR-Data set ready DTR-Data terminal ready RTS-request to send data CTS-Clear to send data TxEMPTY-transmitter empty

8251 Pin Functions

Syndet / BD-Synchronous detect/Break detect In synchronous data transmission the pin will go high if sync characters are detected. In asynchronous transmission the pin will go high if RxD line goes high for more than 2 character times. This indicates an intentional break in transmission

Transmitter Section
Converts 8 bit data to serial data
Transmitter Buffer Output Reg Tx D (Transmit Data)

Transmit Control Logic

Tx C Tx RDY Tx E

Receiver Section
Receives serial data and sends parallel data
Receiver Buffer register Input Reg Rx D (Receives data)

Receiver Control Logic

Rx C Rx RDY Syndet/BD

Initializing 8251
16 bit control register for control word 16 bit status register for checking ready status of input registers To initialize 8251 send a mode word and then a command word to the control register

Mode Word

D7

D6

D5

D4

D3

D2

D1

D0

Framing Control D7 D6 0 0-Not valid 0 1-1Stop bit 1 0-11/2 Stop bit 1 1-2 Stop bit

Parity Control

Character Length

Baud rate factor

D5 D4 D3 D2 D1 D0 x 0- No parity 0 0-5 bits 0 0-Syn Mode 0 1-Odd parity 0 1-6 bits 0 1-Asyn x1 1 1-Even Parity 1 0-7 bits 1 0-Asyn x 16 1 1-8 bits 1 1-Asyn x 64

Control Word
*-Bits for synchronous format modem control
* EH IH *RTS ER *SBRK Rx E *DTE Tx EN

1-Enable search for sync character No effect on asyn mode

Internal Reset

Error Reset 1-Enable 1-reset 1-Enable 0-Disable error flags DTR 1-Enable PE,OE,FE 1-Enable Send Break 0-Disable character 1-forces TxD low

Status Word
DSR-indicates DSR is at low level PE-Set with parity error. Reset with error bit of command word 0E-Set when CPU does not read a character before next is available. FE-Async mode only. Set when valid stop bits is not detected.
DSR SYNDET/ BRKDET FE OE PE TxEMPTY RxRDY TxRDY