ECE-C302

Serial Addition A Finite State Machine

1. Serial Parity Checker 2. Decimal Serial Adder 3. Radix r Serial Adder

1. Serial Parity Checker

X=0 or reset=1

X=1 and reset=0 X=1

x ck reset

even

odd

X=0 or reset=1

Synchronous state machine (clock input ck) States: even or odd number ones appeared at
Port x since a reset (reset=1) z <= 0 when even and 1 when odd

Hardware Description
entity parity_checker is port(x, reset, ck: in std_logic; z: out std_logic); end parity_checker; Architecture behav of parity_checker is Type state is (even, odd); Signal n_s : state; Begin Process(ck) Begin If ck=1 then Case n_s is When even => Z <= 0; If x=1 and reset=0 then n_s <= odd end if;

Decimal Serial Adder

a+b<10 or reset=1

a+b>9 and reset=0 a+b>8

a b
ck reset

No_carry

carry

a+b<9 or reset=1

Operand digits at Port a and b Apply the operands starting from the least
significant digits after a reset State machine with two states

Hardware Description
entity decimal_serial_adder is port( a, b: in integer; reset, ck: in std_logic; z: out integer); end decimal_serial_adder; Architecture behav of decimal_serial_adder is Type state is (no_carry, carry); Signal n_s : state; Begin Process(ck) Begin If ck=1 then Case n_s is When no_carry => Z <= a+b mod 10; If a+b<10 or reset=1 n_s <= no_carry; elsif a+b>9 and reset=0 then n_s <= carry; else null;

Code for Synthesis

Package dec_pack is subtype dec_integer is integer range (0 to 9); End dec_pack; -- use work.dec_pack.all entity decimal_serial_adder is port( a, b: in dec_integer; reset, ck: in std_logic; z: out dec_integer); end decimal_serial_adder; Architecture behav_synth of decimal_serial_adder is Type state is (no_carry, carry); Signal n_s : state; Begin Process(ck) subtype my_integer: integer range(0 to 18); variable temp: my_integer; Begin If ck=1 then Case n_s is When no_carry => temp := a+b; If temp<10 or reset=1 n_s<=no_carry; z<=temp; elsif temp>9 and reset=0 then n_s<=carry; z<=temp-10; else null;

Radix-r Serial Adder

a+b<r or reset=1

a+b>r-1 and reset=0 a+b>r-2

a b
ck reset

No_carry

carry

a+b<r-1 or reset=1

Operand radix-r unsigned at Port a and b

For example, when r = 2 we have binary adder When r = 16 we have hexadecimal adder B + F = 1A (B=11, F=15, 11+15=26 and 26-16=10=A)

Code for Synthesis

Package radixr_pack is subtype radixr_integer is integer range (0 to r-1); End radixr_pack; use work.dec_pack.all; entity radixr_serial_adder is Generic r: natural := 2; port( a, b: in radixr_integer; reset, ck: in std_logic; z: out radixr_integer); end radixr_serial_adder; Architecture behav_synth of radixr_serial_adder is Type state is (no_carry, carry); Signal n_s : state; Begin Process(ck) subtype my_integer is integer range(0 to 2*(r -1)); variable temp: my_integer; Begin If ck=1 then Case n_s is When no_carry => temp := a+b; If temp<r or reset=1 n_s<=no_carry; z<=temp; elsif temp>r-1 and reset=0 then n_s<=carry; z<=temp-r; else null;