VHDL stands for VHSIC Hardware Description Language. VHSIC means Very High Speed Integrated Circuits.

VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as fieldprogrammable gate arrays and integrated circuits. VHDL is an integrated amalgamation of the following languages: Sequential Language + Concurrent Language + Net list Language + Waveform generation language.

VHDL provides 5 different types of primary constructs called Design units. They are: Entity Declaration Architecture Body Configuration Declaration Package Declaration Package Body

Entity Declaration :
Let us examine the syntax rules for an entity declaration and then show some examples. The syntax rules are

entity_declaration entity identifier is [ port ( port_interface_list ) ; ] end [ entity ] [ identifier ] ; interface_list ( identifier { , } : [ mode ] subtype_indication ) { ; } mode in I out I inout

Architecture Body :
The internal operation of a module is described by an architecture body. An architecture body generally applies some operations to values on input ports, generating values to be assigned to output ports. The operations can be described either by processes, which contain sequential statementsoperating on values, or by a collection of components representing sub-circuits. Where the operation requires generation of intermediate values,these can be described using signals, analogous to the internal wires of a module. The syntax rule for architecture bodies shows the general outline: architecture_body architecture identifier of entity_name is { block_declarative_item } begin { concurrent_statement } end [ architecture ] [ identifier ] ;

Configuration:
A configuration is used to bind a component instance to an entity architecture pair. A configuration is like parts list for a design.

Package:
A package is a collection of commonly used data types and subprograms used in a design. Package is just like a tool box that contains tools used to build designs.

Styles of Modeling :
1. Dataflow modeling 2. Behavioral modeling 3. Structural modeling

Dataflow Modeling:
In the dataflow style of modeling, we have to know just about the boolean expressions and how data flows inside the program.

Behavioral Modeling:
For programming in the behavioral style of modeling we have to know about the truth table and behavior of entities in the program.

Structural Modeling:
The structural style of modeling comes into picture when we have to deal with the bigger projects. The big project is divided into small modules and we have to design each module separately. At the end of the project each module is added s the component in the main program, or in other words, all modules are interfaced with each other in the main program.

About XILINX ISE :

Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis,examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

TEST BENCH
A test bench is a model that is used to exercise and verify the correctness of a hardware model.

Entry Level Tool Kit :

The Entry Level Tool - II is a MAX II CPLD (EPM240/570) based board which serves as the basic tool for understanding and experimenting with Programmable Logic Devices, namely the MAX II Family, and hence the name Entry Level Tool - II or ELTII for short. The ELT-II Board helps in understanding the basic Programmable Logic Design flow in the simplest manner. This board contains a number of user IOs for easy access and experimentation.

ELT II BOARD- TOP VIEW :

BOARD COMPONENTS :