ECE2030 Introduction to Computer Engineering Lecture 17: Memory and Programmable Logic

Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

Memory
Random Access Memory (RAM)
Contrary to Serial Access Memory (e.g. Tape) Static Random Access Memory (SRAM)
Data stored so long as Vdd is applied 6-transistors per cell Faster Differential Require periodic refresh Smaller (can be implemented with 1 or 3 transistor) Slower Single-Ended

Dynamic Random Access Memory (DRAM)

Can be read and written Typically, addressable at byte granularity

Read-Only Memory (ROM)

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Block Diagram of Memory

K-bit address lines
K

N-bit Data Input (for Write)

Memory Unit 2k words N-bit per word

N

Read/Write Chip Enable

N-bit Data Output (for Read)

Example: 2MB memory, byte-addressable

N = 8 (because of byte-addressability) K = 21 (1 word = 8-bit)
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Static Random Access Memory (SRAM)

Wordline (WL)

BitLine

BitLine

Typically each bit is implemented with 6 transistors (6T SRAM Cell) During read, the bitline and its inverse are precharged to Vdd (1) before set WL=1 During write, put the value on Bitline and its inverse on Bitline_bar before set WL=1

Dynamic Random Access Memory (DRAM)

Wordline (WL)

Bitline

1-transistor DRAM cell During a write, put value on bitline and then set WL=1 During a read, precharge bitline to Vdd (1) before assert WL to 1 Storage decays, thus requires periodic refreshing (read-sense-write)

Memory Description
Capacity of a memory is described as
# addresses x Word size Examples:
Memory # of addr # of data lines # of addr lines # of total bytes

1M x 8
2M x 4

1,048,576
2,097,152

8
4

20
21

1 MB
1 MB

1K x 4
4M x 32

1024
4,194,304

4
32

10
22

512 B
16 MB

16K x 64

16,384

64

14

128 KB

How to Address Memory

4x8 Memory 2-to-4 Decoder A0 1
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

0
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

2 A1 CS
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

3
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

Chip Select

D7

D6

D5

D4

D3

D2

D1

D0

How to Address Memory

4x8 Memory 2-to-4 Decoder A0=1 1
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

0
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

2 A1=0 3 CS
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

1-bit

1-bit

1-bit

1-bit

1-bit

1-bit

1-bit

1-bit

Chip Select=1
Access address = 0x1

D7

D6

D5

D4

D3

D2

D1

D0

Use 2 Decoders
2-to-4 Decoder A1 Row Decoder 1
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

8x4 Memory 0
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

2 A2 CS
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

3
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

Chip Select

0 1 CS 1-to-2 Decoder Column Decoder

D0 D1 D2 D3

Tristate Buffer (read)

A0

Tristate Buffer
En

Input

Output

Input En Vdd

Output

Similar to Transmission Gate

Could amplify signal (in contrast to a TG) Typically used for signal traveling, e.g. bus
10

Input

En

Output

En

CMOS circuit

Bi-directional Bus using Tri-state Buffer

Direction (control data flow for read/write) A Input/Output

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Read/Write Memory
8x4 Memory 0
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

A1

2-to-4 Row Decoder

1
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

2
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

A2 CS Rd/Wr = 0

3
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

Chip Select = 0

CS

1 1-to-2 Column Decoder

D0 D1 D2 D3

A0

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Read/Write Memory
8x4 Memory 0
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

A1

2-to-4 Row Decoder

1
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

2
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

A2 CS Rd/Wr = 1

3
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

Chip Select = 1

CS

1 1-to-2 Column Decoder

D0 D1 D2 D3

A0

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Building Memory in Hierarchy

Design a 1Mx8 using 1Mx4 memory chips
D7 1Mx4
R/W

D6
D5 D4

CS

A19 A18 A17

A19 A18 A17

D3

1Mx4
A0 A0
CS R/W

D2

D1
D0

CS

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Building Memory in Hierarchy

Design a 2Mx4 using 1Mx4 memory chips
Note that 1-to-2 decoder is the wire itself (or use an inverter) A19 A18 A17 1Mx4 A0 A20
1-to-2 Decoder
1 0

D3

D2
D1 D0

CS

R/W

CS

A19 A18 A17 1Mx4 A0

R/W

CS

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Building Memory in Hierarchy

Design a 2Mx8 using 1Mx4 memory chips
A19 A18 A17
A0 A20
1-to-2 Decoder
1
0
A0 CS R/W A19 A18 A17 A19 A18 A17

D7
1Mx4 CS R/W

D6 D5 D4 D3 D2

A0 A19 A18 A17

1Mx4

D1
D0

CS

1Mx4 CS R/W

A0 A19 A18 A17

1Mx4 CS R/W
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A0

Memory Model
32-bit address space can address up to 4GB (232) different memory locations
0x00000000 0x00000001 0x00000002

0x0A
0xB6 0x41

Lower Memory Address

0x00000003

0xFC

0xFFFFFFFF

0x0D

Higher Memory Address

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Flat Memory Model

Endianness [Danny Cohen 91]

Byte ordering How a multiple byte data word stored in memory Endianness (from Gullivers Travels)
Big Endian
Most significant byte of a multi-byte word is stored at the lowest memory address e.g. Sun Sparc, PowerPC

Little Endian
Least significant byte of a multi-byte word is stored at the lowest memory address e.g. Intel x86

Some embedded & DSP processors would support both for interoperability
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Endianness Examples
Store 0x87654321 at address 0x0000, byte-addressable
0x0000 0x0001 0x0002

0x87
0x65 0x43

Lower Memory Address

0x0000 0x0001 0x0002

0x21
0x43 0x65

Lower Memory Address

0x0003

0x21

0x0003

0x87

Higher Memory Address

BIG ENDIAN LITTLE ENDIAN

Higher Memory Address

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Memory Allocation (Little Endian)

declare: .data .globl declare .align 0 .word 511 .byte 14 .align 2 .byte 14 .word 0x0B1E8143 .align 2 .ascii GAece .half 10 .word 0x2B1E8145 .space 1 .byte 52 .align 1 .byte 16 .space 2 .byte 67
0 1 2 3 4 5 6 7 8 9 a b c d

0xFF 0x01 0x00 0x00 0x0E ------

e f 10 11 12 13

----------0x47 0x41 0x65 0x63 0x65 0x0A 0x00 0x45

1c 1d 1e 1f

0x34 -----0x10

20
21

0x43

----------0x0E 0x43

14
15

.align N: Align next datum on a 2n byte boundary

.align 0: turn off automatic alignment for .half, .word, .float, and .double till the next .data directive .word: 4 bytes .half: 2 bytes .byte: 1 byte .space: 1-byte space .ascii: ASCII code (American Standard Code for Information Interchange) 20

16
17 18 19 1a 1b

0x81
0x1E 0x0B ------

0x81
0x1E 0x2B

Read Only Memory (ROM)

Permanent binary information is stored Non-volatile memory
Power off does not erase information stored

K-bit address lines

K

ROM
2k words N-bit per work

N-bit Data Output

N

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32x8 ROM
5 A4 A3 A2 A1 A0 5-to-32 Decoder
28 29 30 31 0 1 2 3

32x8 ROM

Each represents 32 wires

Fuse can be implemented as a diode or a pass transistor

D7

D6

D5

D4

D3

D2

D1

D0
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Programming the 32x8 ROM

A4 0 0 0 1 A3 0 0 0 1 A2 0 0 0 1 A1 0 0 1 0 A0 0 1 0 1 D7 1 1 1 0 D6 1 0 0 0 D5 0 0 1 0 D4 0 0 1 1 D3 0 1 0 0 D2 1 0 0 0 D1 0 1 0 0 D0 1 1 0 0

1
1

1
1

1
1

1
1

0
1

0
1

1
1

0
1

1
0

0
0

1
0

1
0

0
1

A4 A3 A2 5-to-32 Decoder

0 1 2

A1 A0

29 30 31

D7 D6 D5 D4 D3 D2 D1 D0

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Example: Lookup Table

Design a square lookup table for F(X) = X2 using ROM

X 0 1 2 3 4 5 6 7

F(X)=X2 0 1 4 9 16 25 36 49

X 000 001 010 011 100 101 110 111

F(X)=X2 000000 000001 000100 001001 010000 011001 100100 110001

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Square Lookup Table using ROM

0 X 000 001 010 011 100 101 110 111 F(X)=X2 000000 000001 000100 001001 010000 011001 100100 110001 1

X2 X1 X0

3-to-8 Decoder

2 3 4 5 6 7

F5

F4

F3

F2

F1

F0

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Square Lookup Table using ROM

0 X 000 001 010 011 100 101 110 111 F(X)=X2 000000 000001 000100 001001 010000 011001 100100 110001 1

X2 X1 X0

3-to-8 Decoder

2 3 4 5 6 7

F5

F4

F3

F2

F1

F0
= X0

Not Used

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Square Lookup Table using ROM

0 1

X
000 001 010 011 100 101 110 111

F(X)=X2
000000 000001 000100 001001 010000 011001 100100 110001

X2 X1 X0

3-to-8 Decoder

2 3 4 5 6 7

F5

F4

F3

F2

F1

F0

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Classifying Three Basic PLDs

INPUT Fixed AND plane (decoder) Programmable Connections Programmable OR plane

OUTPUT

(Programmable) Read-Only Memory (ROM) Programmable AND plane Programmable Connections Programmable OR plane

INPUT

OUTPUT

Programmable Logic Array (PLA) Programmable AND plane Fixed OR plane

F/F OUTPUT

INPUT

Programmable Array Logic (PAL) Devices

PAL: trademark of AMD, use PAL as an adjective or expect to receive a letter from AMDs lawyers
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Programmable Logic Array (PLA)

A B C Programmable OR Plane

Programmable AND Plane C C B B A A

F2
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Example using PLA

F1(A, B, C) m(0,1,2,4) F2(A, B, C) m(0,5,6,7)

F1 A B AC BC F1 AB AC BC F2 AB AC A BC
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Example using PLA

A B C AB AC BC ABC C C B B A A F1

F1 AB AC BC F2 AB AC A BC

F2
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PAL Device
A Programmable AND Plane A A B B IO1 IO2 IO1 IO1 IO1

IO2

B Fixed OR Plane

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PAL Device Design Example

A A B B C C D D IO1 IO1 IO1
Not programmed

IO2

IO1 ABC A BCD IO2 ABC A BCD ACD A BCD

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CPLD and FPGA [Brown&Rose 96]

Complex Programmable Logic Device (CPLD)
Multiple PLDs (e.g. PALs, PLAs) with programmable interconnection structure Pioneered by Altera

Field-Programmable Gate Array (FPGA)

High logic capacity with large distributed interconnection structure
Logic capacity number of 2-input NAND gates

Offers more narrow logic resources

CPLD offers logic resources w/ a wide number of inputs (AND planes)

Offer a higher ratio of Flip-flops to logic resources than CPLD

HCPLD (High Capacity PLD) is often used to refer to both CPLD and FPGA
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CPLD structure
Logic block

PLD

PLD

PLD

PLD

I/O block

Interconnects

PLD

PLD

PLD

PLD

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FPGA Structure
Logic block

I/O block

Interconnects

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FPGA Programmability
Floating gate transistor
Used in EPROM and EEPROM

SRAM-controlled switch Control

Pass transistors Multiplexers (to determine how to route inputs)

Antifuse
Similar to fuse Originally an Open-Circuit One-Time Programmable (OTP)
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