SUPARNA RAJ PETLURI MTECH (VLSI) 1221210127

The phase-locked-loop (PLL) is widely used in many systems for frequency synthesis, lock/data recovery, clock de-skewing, and so on. The principle of a PLL is to compare the frequency and phase difference between two signals, ensuring that they are synchronized. When the phase error between two signals is equal or close to zero, it is called locked. Currently, the most commonly adopted structure is so-called digital PLL, whose loop filter and voltage-controlled oscillator (VCO) are actually analog though. Nevertheless, with the fast advances in integrated circuit technology and the fabrication processes, digital circuits are much more preferred than analog circuits in most applications, since a digital design is scalable and easy to be redesign or shrunk while changing process. Therefore, in an alldigital PLL (ADPLL), the analog loop filter is replaced by a digital filter, and the analog VCO is replaced by a digitally controlled oscillator (DCO). In addition, the noisesensitive issue of a VCO can be improved by using a DCO, which inherently is more immune to noise.

The presented ADPLL was designed based on a well known type-II, secondorder charge-pump PLL. The advantage of this design procedure is that it is easy to redesign the circuit with the only need of analyzing the frequency response for stability issue.

the block diagrams of the presented ADPLL, which consists of a phase-todigital converter (P2D), a digital low-pass filter (LPF), a DCO, and a divider. The P2D is used to sense the phase difference between the input reference clock and the divided DCO clock, and then convert it to a digital format. The digital LPF filters out the undesired high-frequency signals to stabilize the DCO.

The P2D includes the circuits of a phase and frequency detector (PFD), a time-to-digital converter (TDC), a decoder, and some logic gates. Then, the TDC digitizes the offtime width t of the pulse into a set of binary digits with a resolution of TDC. And the decoder is used to decode those binary digits to their corresponding digital numbers for the following digital LPF.

Phase frequency detector is one of the important parts in PLL circuits. PFD (Phase Frequency Detector) is a circuit that measures the phase and frequency difference between two signals, i.e. the signal that comes from the VCO and the reference signal. PFD has two outputs UP and DOWN which are signaled according to the phase and frequency difference of the input signals.

Dynamic-logic PFD is used instead of a normal static-logic PFD, the number of transistors in the dynamic PFD is reduced from 44 to 16. The critical path of this PFD is only composed of three gates. As a result, the dynamic PFD overcomes the speed limitation and reduces the dead zone. The signals UP and DN are combined by an NOR gate to produce its output signal PFD_out, whose off-time width is proportional to the absolute value of the phase error.

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