INTELs TriGate SOI (SSDM 2002)

Highest ever performance reported for NMOS and PMOS devices on a single substrate !!
Semiconductor Device Modeling for VLSI 1

INTEL TriGate Results (2002- till date)

LG = 15nm
Semiconductor Device Modeling for VLSI

LG = 60nm, TSi = 36nm and WSi = 55nm

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TSMCs -gate Device (SSDM-2002)

Semiconductor Device Modeling for VLSI

Research Work at TSMC (2002)

Semiconductor Device Modeling for VLSI

Multi-Body Single-Gate Devices

Front-View

Body

G A T E

Multi-Body Single gate devices an attractive option. Increased current drive using a single gate. Total current nearly equals the current thru one body multiplied by the number of body regions. Fabrication feasibility. Feasible for the Dual-Gate, Tri-Gate and -gate devices.
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Top-View
Semiconductor Device Modeling for VLSI

Device Design (A brief Summary)

Research Initiative Devices under investigation completely novel. Only N-channel devices investigated to some extent. Device structural variations and their effect on performance investigated to a minor degree. Microwave performance of the devices not investigated at all.

Modeling Approach at U.C. (Semiconductor Devices Laboratory) Numerical device simulators from SILVACO International and ISE. Extensive 3-D modeling of the four N-channel device structures. P-channel devices to be modeled in succession. RF analysis of the N-channel devices followed by the P-channel devices, extraction of important device parameters. Effect of temperature variation on device performance to be analyzed.
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Semiconductor Device Modeling for VLSI

Preliminary Results and Future Work

Semiconductor Device Modeling for VLSI

Multi-Gate SOI MOSFETs (3-D Views)

Double Gate/ FinFET TriGate

-Gate
Semiconductor Device Modeling for VLSI 8

QuadGate

Multi-Gate SOI MOSFETs (2-D Cutplane Views)

Double-gate/ FinFET TriGate

-Gate

QuadGate

Note: Symmetric and Asymmetric devices possible

Semiconductor Device Modeling for VLSI 9

The -Gate Transistor (The Pseudo 4th gate)

Physics of operation difficult to understand. Lies somewhere in between a TriGate and a Quadruple-gate device as regards structure. Virtual presence of a back-gate in oxide layer that acts as a pseudofourth gate.
Virtual Back Gate

Presence of the virtual gate prevents electric field lines from the drain from penetrating the channel. Amount of vertical gate polysilicon penetration a design factor.
Semiconductor Device Modeling for VLSI 10

PiGate Transistor (Vertical Gate Penetration Simulation)

Baseline device dimensions Gate Length = 50 nm Body Width = 50 nm Body Height = 50 nm Channel Doping = 1x1016 /cm3 Source/ Drain Doping = 1x1019 /cm3 Oxide Thickness = 2 nm Gate Workfunction = 4.6 eV

N-type devices considered. 50-100nm technology node well developed and has translated into a manufacturable technology. Too shallow or too deep an etch in the oxide necessitates accuracy and also poses stringent fabrication tolerances. Optimum value of 50 nm chosen as the vertical polysilicon penetration depth.

Semiconductor Device Modeling for VLSI

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Drain-Current (ID - VDS) Characteristics

FinFET

TriGate

PiGate

QuadGate

Semiconductor Device Modeling for VLSI

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Gate (ID - VGS) Characteristics (FinFET and TriGate)

FinFET Device Characteristics Threshold Voltage = 0.196 V Subthreshold Slope = 72 mV/decade Off Current = 70 A/m DIBL = 64.67 mV/V

FinFET TriGate Omega-Gate Quadruple-Gate

Semiconductor Device Modeling for VLSI 13

TriGate Device Characteristics Threshold Voltage = 0.179 V Subthreshold Slope = 84 mV/decade Off Current = 37.09 A/m DIBL = 75.11 mV/V

Gate (ID - VGS) Characteristics (-gate and Quadruple-gate)

-Gate Device Characteristics Threshold Voltage = 0.193 V Subthreshold Slope = 68.08 mV/decade Off Current = 55.82 A/m DIBL = 134.9 mV/V
FinFET TriGate

Omega-Gate
Quadruple-Gate

Quadruple-Gate Device Characteristics Threshold Voltage = 0.198 V Subthreshold Slope = 65 mV/decade Off Current = 50 A/m DIBL = 100.74 mV/V
Semiconductor Device Modeling for VLSI 14

Device Structural Variations (Gate Length)

FinFET TriGate -Gate Quad-Gate

J-T. Park and J-P Colinge, IEEE Transactions on Electron Devices, pp. 2222-2228, vol. 49, no. 12, Dec. 2002.

Device Dimensions
Fin Width = 50 nm Channel Doping = 1x 1016 /cm3 Workfunction = 4.6 eV Oxide Thickness = 2 nm

Subthreshold Slope = 70-80 mV/decade and lower for switching applications. Number of gates does influence device operation.

A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

Semiconductor Device Modeling for VLSI

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Device Structural Variations (Channel Doping)

FinFET TriGate -Gate Quad-Gate

J-T. Park and J-P Colinge, IEEE Transactions on Electron Devices, pp. 2222-2228, vol. 49, no. 12, Dec. 2002.

Near identical behavior in both graphs. Channel doping normally maintained at a low value to minimize effects of scattering. Mobility degradation observed at high values of channel doping. Moderate levels of channel doping could be used.

Device Dimensions
Fin Height/Width = 50 nm Gate Length = 50 nm Workfunction = 4.6 eV Oxide Thickness = 2 nm

A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

Semiconductor Device Modeling for VLSI

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Device Structural Variations (Gate Length and Channel Doping)

FinFET TriGate -Gate Quad-Gate

Threshold voltage decreases with decrease in gate length, short-channel effect seen to exist in these devices. Threshold voltage sensitive to channel doping beyond 1x10 16 /cm3. Can we use channel doping to tailor threshold voltage?

Device Dimensions
Fin Height = 50 nm Fin Height = 50 nm Workfunction = 4.6 eV Oxide Thickness = 2 nm

A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

Semiconductor Device Modeling for VLSI

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Device Dimension Variations (Fin Height)

FinFET TriGate -Gate Quad-Gate

Device Dimensions
Gate Length = 50 nm Channel Doping = 1x1016 /cm3 Workfunction = 4.6 eV Oxide Thickness = 2 nm Fin Width = 50 nm
A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

Semiconductor Device Modeling for VLSI

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Device Dimension Variations (Fin Width)

FinFET TriGate -Gate Quad-Gate

Device Dimensions
Gate Length = 50 nm Channel Doping = 1x1016 /cm3 Workfunction = 4.6 eV Oxide Thickness = 2 nm Fin Height = 50 nm
A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

Semiconductor Device Modeling for VLSI

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Device Design Parameters

FinFET TriGate

-Gate
Quad-Gate

Important step in device design is not patterning of gate region , but instead it is the patterning of the body width. Ideally increase in the number of gates provides an improvement in performance.

Device Dimensions
Workfunction = 4.6 eV Oxide thickness = 2 nm

Semiconductor Device Modeling for VLSI

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Device Design Parameters (..cont.)

FinFET TriGate

-Gate
Quad-Gate

TriGate variation minimal when Fin Width is considered. Ideal Gate Length/ Fin Width ratio for FinFET is 1.3 or higher, for a TriGate is unity or higher, for a -gate it is 0.8 or higher and for a Quadruple-gate it is 0.6 or higher.

Semiconductor Device Modeling for VLSI

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Effect of Variation in Gate Oxide Thickness

FinFET TriGate -Gate
Device Dimensions
Channel Doping = 1x1016 /cm3 Fin Width = 50 nm Fin Height = 50 nm Gate Length = 50 nm Gate Workfunction = 4.6 eV

QuadGate

Thinner oxides with higher dielectric constants could be looked upon as an alternative for either device. (Hints at the need to look into new materials (HfO2, ZrO2) as a substitute for SiO2 in nanoscale devices).
A. Breed and K.P. Roenker, pp. 150-151, International Semiconductor Device Research Symposium, 2001.

Semiconductor Device Modeling for VLSI

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MOSFET Microwave Performance

Silicon-only planar MOSFETs are under consideration. Devices below 200nm gate length are experimental devices. All devices can be optimized for either a larger cut-off frequency or a larger maximum frequency of operation. No strained technology used for MOSFET fabrication.
Juin J. Liou and Frank Schwierz, Solid State Electronics, pp. 1881-1895, vol. 47, 2003.

Semiconductor Device Modeling for VLSI

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Current Gain (h21) & Unilateral Power Gain (UMax)

FinFET TriGate

Gate Bias = 0.8 Volts

TriGate FinFET

TriGate

FinFET

Legend

Current Gain Unilateral Power Gain

Identical behavior for the FinFET and TriGate transistors. TriGate performance again superior to the FinFET. Overall device performance better than that of a planar MOSFET !!
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A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.

Semiconductor Device Modeling for VLSI

Variation in the Cutoff Frequency (fT)

TriGate FinFET
Gate Bias = 0.8 Volts

TriGate

FinFET

Similar variation of fT with gate bias and frequency exhibited by the FinFET and TriGate transistors. TriGate exhibits a peak value of 51.5 GHz and the FinFET a peak value of 42.2 GHz for the cut-off frequency. TriGate is superior again compared to the FinFET (nearly a 20% improvement)!! Values however less than that reported for an optimized planar RF MOSFET transistor (178 GHz - J-J. Liou et. al, Solid State Elec., vol. 47, 1881-1895, 2003).
A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.

Semiconductor Device Modeling for VLSI

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Variation in the Maximum Frequency of Oscillation (FMax)

Gate Bias = 0.8 Volts

TriGate

TriGate

FinFET FinFET

Similar variation of fMax with gate bias and frequency exhibited by the FinFET and TriGate transistors. TriGate exhibits a peak value of 228 GHz and the FinFET a peak value of 183 GHz. TriGate is superior again compared to the FinFET (20% improvement)!! TriGate performs even better than a planar RF transistor (193 GHz - J-J. Liou et. al, Solid State Elec., vol. 47, 1881-1895, 2003) !!
A. Breed and K.P. Roenker, IEEE Conference on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, GA 2001.

Semiconductor Device Modeling for VLSI

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Conclusions and Future Work

Conclusions:
Successfully modeled devices in 3-dimensions. Understood device design space and scaling constraints. Undertook a study to understand fabrication tolerances to which every device could be exposed. Both subthreshold and RF performance explored.

Future Work:
Model p-channel devices, scaling rules could differ. Understand device design in totality given a variation in two or more than two parameters. Investigate their Microwave characteristics. Comparison with n-channel performance for CMOS and BiCMOS incorporation. Understand effects of temperature on device performance.

Semiconductor Device Modeling for VLSI

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References 1. A. Breed and K.P. Roenker, Dual-gate (FinFET) and TriGate MOSFETs: Simulation and design, Proceedings of the International Semiconductor Device Research Symposium (ISDRS-2003), pp. 150-151, December 2003. J-T. Park and J-P Colinge, Multiple-Gate SOI MOSFETs: Device Design Guidelines, IEEE Transactions on Electron Devices, pp. 2222-2228, vol. 49, no. 12, Dec. 2002. Aniket Breed and Kenneth P. Roenker, A Small-signal, RF Simulation Study of Multiple-gate MOSFET Devices, IEEE Topical Meeting on Silicon Monolithic ICs in RF Systems, Atlanta, GA, Sept. 2004.
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2.

3.

Semiconductor Device Modeling for VLSI