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1. 8086 (definition + specification).....................03 2. Comparison b/w 8085 & 808605 3. Architecture of 808606 4. Registers of 8086..09 5. Advantages of Segmented memory16 6. Addressing modes of 808617 7. Pin Diagram24 8. Instructions of 8086.28 9. Conclusion.36
Key Features:
Released by Intel in 1978 Produced from 1978 to 1990s A 16-bit microprocessor chip. Max. CPU clock rate : 5 MHz to 10 MHz Instruction set: x86-16 Package: 40 pin DIP Intel 8086 Microprocessor The 8086 gave rise to the x86 architecture of Intel's future processors. Common manufacturer(s): Intel, AMD, NEC, Fujitsu, Harris (Intersil), OKI, Siemens AG, Texas Instruments, Mitsubishi.
8086
Created in 1978 16-bit processor 16-bit data bus 16-bit general purpose register 20-bit address bus It can access 1 MB of memory Complex Architecture Clock speed is 5Mhz More operational instructions No. of Flags=9
ARCHITECTURE OF 8086
EU (EXECUTION UNIT)
Read instructions from Queue, Decode & Execute. 16-bit Arithmetic unit, 16-bit flag Register, four General purpose Register, four 16-bit offset Register. Pipelining (The process of fetching the next instruction while the current instruction is executing).
REGISTERS OF 8086
FLAG REGISTER
O D I T S Z AC P CY
FLAG REGISTER
1.
2. 3. 4. 5. 6. 7. 8. 9.
CY (Carry Flag) P (Parity Flag) AC (Auxiliary Carry Flag) Z (Zero Flag) S (Sign flag) OF (Overflow Flag) DF (Direction Flag) IF (Interrupt Flag) TF (Trap Flag)
SEGMENT REGISTER
1.Code Segment (CS) 2.Data Segment (DS) 3.Stack Segment (SS) 4.Extra Segment (ES)
OFFSET REGISTER
1.Instruction Pointer (IP) 2.Stack Pointer (SP) 3.Source Index (SI) 4.Destination Index (DI) 5.Base Pointer (BP)
ADVANTAGES OF SEGMENTED MEMORY To Form 20-bit memory Address Program can work on different set of Data Program can be loaded or executed anywhere in the memory In multitasking environment, different programs may run simultaneously on different terminal using the common processor and memory, by reloading the contents of various segment Registers for each program.
REGISTER ADDRESSING
MOV AX, BX
IMMEDIATE ADDRESSING
The Data remains in the part of the instruction
DIRECT ADDRESSING
The memory Offset address is directly available in the instruction.
INDIRECT ADDRESSING
Memory Offset address is specified in some Microprocessor Register, Various Combinations are possible.
MOV DX, [SI] MOV DL, [SI+12] MOV DL, [BP-25] MOV [BP+SI], DH
STRING ADDRESSING
Special Instructions are available to handle Strings The m/m address of the source Data is specified by DS:SI The m/m address of the destination data By ES:DI
PORT ADDRESSING
To read Data from an input port
IN AL, 42H
To write Data to an output port OUT 25H, AL
INSTRUCTIONS OF 8086
1. Data copy Instructions 2. Arithmetic Instructions 3. Logical Instructions 4. Arithmetic Adjust Instructions 5. String Instructions 6. Branch Instructions 7. Machine Control Instructions 8. Instructions Related to Stack
ARITHMETIC INSTRUCTIONS
1. ADD operand1, operand2 2. ADC operand1, operand2 3. SUB operand1, operand2 4. SBB operand1, operand2 5. INC operand 6. DEC operand 7. NEG operand 8. CMP operand1, operand2 9. MUL operand 10. IMUL operand 11. DIV operand 12. IDIV operand
LOGICAL INSTRUCTIONS
1. AND operand1, operand2 2. OR operand1, operand2 3. XOR operand1, operand2 4. TEST operand1, operand2 5. NOT operand 6. SAL/SHL operand, count 7. SAR operand, count 8. SHR operand, count 9. RCL operand, count 10. RCR operand, count 11. ROL operand, count 12. ROR operand, count
STRING INSTRUCTIONS
1. STOSB 2. STOSW 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. STOS offset LODSB LODSW LODS offset MOVSB MOVSW MOV offset1, offset2 SCASB SCASW SCAS offset CMPSB CMPSW CMPS offset
BRANCH INSTRUCTIONS
1. Jump Instructions ( Near jump, Far jump, unconditional jump, Conditional jump 2. Loop Instructions (LOOP label) 3. Call and Return Instructions (LOOPNE/LOOPNZ short target) 4. Software Interrupt Instructions ( INT n)