AUTOMOTIVE EMBEDDED SYSTEMS

VIJAY UPADHYAY

11AT61R06

FUNCTIONS OF AUTOMOTIVE EMBEDDED SYSTEMS

Powertrain Control Functions
E n g i n e c o ntro l f o r f u e l e ff i cien cy. H yb ri d S ys te m , H a rd R e a l Ti m e (m i c ro ,m illis ec ond s).

Chassis Control
B ra ki n g , S u sp e n sion , S te e ri n g , S ta b i l ity. A B S ,E SP, B y wi re . H yb ri d S ys te m , H a rd R e a l Ti m e (m illisec on ds ).

Body Electronics
L i g h ts , d o o rs , wi n d o ws , d a s h b o a rd , s e a ts , m i rro rs . D i s c re te , R e a c ti v e (s e co nds ).

Telematics
N a vi g atio n, i n f o ta inme nt , re m o te v e h i cl e d i a g n o stics . H a n d s f ree p ho ne , ra d i o , C D , D V D .
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AUTOMOTIVE COMMUNICATION SYSTEM

For better control proper communication is required. SAE classified automotive comm. protocols based on data transmission speed
 CLASS A -- Data rate less than 10 kb/s. -- Transmit simple control signals and used in Body domain. -- Class A networks are LIN and TTP/A.  CLASS B -- Data rate 10 kb/s to 125 kb/s. -- Supports data exchange between ECUs. -- For Class B applications low-speed CANs are used.  CLASS C -- Data rate 125 kb/s to 1 Mb/s. -- Used for Powertrain and Chassis domain. -- High speed CAN is used.  CLASS D Data rate greater than 1 Mb/s. -- For multimedia data (e.g. MOST) and x-by-wire applications requiring predictability & fault tolerance (e.g. TTP/C).
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MODE OF COMMUNICATION
Event Triggered
Event triggered networks are non-deterministic. Signals are transmitted indicating occurrence of significant event. Protocol adopts a particular scheme to avoid collision. Efficient in terms of bandwidth. Evolution of system without redesigning existing nodes is generally possible.  Fast reaction to asynchronous events occurring at unknown times.  No time synchronization between network node hence delay occurs due to media access and queuing mechanisms.  Traffic from non-safety-critical multimedia applications is considered as event-triggered traffic.     
w aiting time for B

event A

event B

MODE OF COMMUNICATION(CONT.)
Time Triggered
 Frames are transmitted at predetermined points in time.  As frame scheduling is predefined, timing constraints are easier to check.  Missing messages can be immediately identified thus nodes that are not operational.  Not flexible to unplanned addition of a new transmitting node on the network.  FOR data transmission in respective time slots, network elements designed for minimal delay times without queues.  Traffic in time-triggered systems is small compared to that in event-triggered.  Allowed delay and jitter for time-triggered traffic is larger.
time slot

C
Cycle Time

t
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CONTROLLER AREA NETWORK (CAN)

CAN has the following properties
       Prioritization of messages Configuration flexibility Multicast reception with time synchronization System wide data consistency Multimaster Error detection and signalling Supports real-time control with a very high level of security.

DATA TRANSMISSION PROTOCOL IN CAN

Application Layer
- Upper level comm. functions of OSI model

Object Layer
- Message filtering - Message and Status Handling - Fault Confinement - Error detection and Signalling - Message Validation - Acknowledgment - Arbitration - Message Framing - Transfer Rate and Timing

Transfer Layer

Physical Layer
- Signal Level and Bit Representation - Transmission Medium
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CAN DATA FRAME

CAN Data Frame Structure

SOF - o n e Header

d o m i n an t b i t i s s e n t to i n d i c a te th e s ta rti n g o f d a ta f ra m e .

 Identifier - defines message priorities during arbitration. - CAN bus operates as an AND operator.  RTR this bit shows whether data is being sent to destination or the
destination node is requesting for data to source.

 DLC - indicates no of bytes in data field.

CAN DATA FRAME (CONTD.)

Data CRC
i t c o n ta i n s d a ta b e i n g tra n s m i tte d b e twe e n d i ff e re nt n o d e s .

 CRC SEQUENCE - this part of CRC field is actually used for error detection and correction .  CRC DELIMITER - The CRC SEQUENCE is followed by the CRC
DELIMITER which consists of a single recessive bit.

ACK - i t co n ta i n s th e A C K S L OT a n d th e A C K D E L IMIT E R . - i n b o th A C K f i e l d s th e tra n s m i tte r s e n d s re c e s s i v e b i ts

s h o wi n g

co m p l e tion o f tra n s m i s s ion. - re c e i v e r re p o rts e rro r f re e re ce p ti o n b y s e n d i n g a d o m i na nt b it d u ri n g th e A C K S L OT

EOF b i ts.

E a c h D ATA F R A ME i s d e l i mite d b y a s e q u e n c e o f s e ve n re c e s s i ve a vo i d s th e f ra m e i n te rf e re n ce .
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Interframe Space

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MEDIA ORIENTED SYSTEM TRANSPORT (MOST)

MOST is used f or applications requiring high data transmission rate.
In a MOST network one MOST device handles the role of the Timing Master. Master supplies the clock with a synchronous and continuous data signal and all other devices synchronize their operation to this base signal. Synchronization eliminates the need of buffering and sampling rate conversion. The MOSTs physical layer supports plastic optical f ibre transmission which provides better resilience to EMI.

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ARCHITECTURES IN TIME-CRITICAL EMBEDDED SYSTEMS

Automotive domain requier many time-critical applications. A schedulability analysis needs to be done to f ind W CET and BCET.

Timing Analysis Framework- there are three major building blocks

 Control-flow reconstruction and static analyses for control and data flow;  Micro-architectural analysis, which computes upper and lower bounds on execution times of basic blocks;  Global bound analysis, which computes upper and lower bounds for the whole program.

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COMPONENTS OF TIMING ANALYSIS FRAMEWORK

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COMPONENTS OF TIMING ANALYSIS FRAMEWORK

Control-flow reconstruction
 Takes a binary executable to be analysed.  Transforms the program into a suitable intermediate representation.  Problems encountered are dynamically computed control-flow successors.

Value analysis
 Computes an approximation of the set of possible values in registers and memory locations by an interval analysis.

Loop bound analysis

 identifies loops in the program and tries to determine bounds on the number of loop iterations.  Problems are the analysis of arithmetic on loop counters and loop-exit conditions, as well as dependencies in nested loops. 14

COMPONENTS OF TIMING ANALYSIS FRAMEWORK

Control flow analysis
 Narrows down the set of possible paths through the program by eliminating infeasible paths.  Determine correlations between the number of executions of different blocks.  These constraints will tighten the obtained timing bounds.

Micro-architectural analysis
 Determines bounds on the execution time of basic blocks.  Static cache analyses determine safe approximations to the contents of caches at each program point.  Pipeline analysis analyses how instructions pass through the pipeline accounting for occupancy of shared resources like queues, functional units etc.
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COMPONENTS OF TIMING ANALYSIS FRAMEWORK

Global bound analysis
 Determines bounds on execution time for the whole program.  Information about the execution time of basic blocks is combined to compute the shortest and the longest paths through the program.  This phase takes information provided by the loop bound and controlflow analyses.

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ARCHITECTURE OF THE SYSTEM

RAM

High Speed A/D Acquisition



CPLD

DSP
HPI 32

ARM realtime display

LCD and Touch screen

RAM

data stream

signal stream control signal

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AUTOMOTIVE ENGINE ANALYSER SOFTWARE PLATFORM

The main functions of the software system are
 displaying figures and texts on LCD (including menu setting),  touch screen functions,  communication between HPI32 and DSP,  refreshing waveform on LCD. All these tasks need to be performed simultaneously.

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GENERAL FLOW CHART OF SOFTWARE

Power on resetting

Board initialization System booting/upgrade System initialisation

Application initialization

Multitask application
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THE MENU TREE

Level One Menu

Level Tow Menu 1

Level Tow Menu n

Level Three Menu 1

Level Three Menu n

Level Four Menu 1

Level Four Menu n

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FLOW CHART OF THE TOUCH SCREEN MENU TASK

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FLOW CHART OF THE DSP TASK

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REAL-TIME OPERATING SYSTEM

VRTX
 VRTX is a real-time operating system.  In VRTX many routines can run in parallel.  Each routine is an infinite loop, in which the routine waits for specific inputs and then executes corresponding tasks.  For parallel execution VRTX divides the system in relatively simple and cooperative modules.

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VRTX ARCHITECTURE

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VRTX ARCHITECTURE (CONTD.)

A small run time implements interrupt handling, memory allocation, event queuing and scheduling and f ine-grained spin-locks f or synchronisation between CPUs. Rest of the system is implemented within modules called stages. Stages maintain their own data structure and communicate with one another exclusively with events. Each stage has its own event handler. These stages cannot share memory.

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REFERENCES
R o b e rt B o sc h Gm b H . C A N S p e c i fic atio n, Ve rs i o n 2 .0 , 1 9 9 1 . A . A l b e rt, C o m p a ris on o f e v e n t-tri g g ere d a n d ti m e -tri g ge red c o n c e p ts wi th re g a rd s to d i stri b u te d c on trol s yste m s, p re s e n te d a t th e E m b e d d ed W orld C o n f . 2 0 0 4 , N rn b e rg , Ge rm a n y, 2 0 0 4 . G. L e e n a n d D . H e ff e rn an, E xp a n d i ng a u to m o ti v e e l e c tro n i c s ys te m s , IE E E C o mp u t., v o l . 3 5 , n o . 1 , p p . 8 8 9 3 , J a n . 2 0 0 2 . W e i Yi n g yi n g a n d C a i Qi z h o n g R e s e a rch a n d D e s i g n o f th e E m b e d d ed S o f twa re S ys te m o f A u to m o ti ve E n g i n e A nalys e r p re s e n te d a t T h e E i g h th In te rn a ti o nal Co nfe ren ce o n E l e c tro n ic Me a s ure men t a n d In s tru m e n ts 2 0 0 7 . A g e K a l n e s , D a g J o h a n s e n , U n i v e rs ity o f Tro m s o , N o rwa y V ORT E X: a n e v e n t-d riv en m u l ti p roc es so r o p e ra ti n g s ys te m s u p p o rti ng p e rf o rm a nc e i s o l atio n 2 0 0 3 .
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REFERENCES (CONTD.)
R e i n hard W ilhelm, D a n i e l Gru n d , J a n R e i n e ke, Ma rc S c h l i ck ling , Ma rk u s P i s te r, a n d C h ri sti a n F e rd i n a nd Me m o ry H i e ra rc hie s, P i p e lin es , a n d B u se s f o r F u tu re A rch i te c tu res i n Ti m e -C ritic al E m b e d d ed S ys te m s IE E E T R A NSACTION S ON C OMP U T E R -AIDED D E S IGN OF IN T E GR ATED C IR C UITS A ND S YSTEMS , V OL . 2 8 , N O. 7 , JU LY 2 0 0 9 . G. B e rn a t, A . C o l i n , a n d S . M. P e tte rs, W CET a n a l ys i s o f p ro b a b i listic h a rd re a l -ti me sys te m s , i n P ro c . 2 3 rd IE E E RT S S , 2 0 0 2 , p p . 2 7 9 2 8 8 . N IC OL A S N AV E T, Y E QION G S ON G, F R A NOIS E S IMON OT-L ION , A N D C D RIC W ILW ERT Tren ds in Au to mo tive C o mmu n ic a tion S ys te ms IE E E , V OL . 9 3 , N O. 6 , J U N E 2 0 0 5 . Te xa s In s tru m e n ts A p p l i c atio n R e p o rt S L L A 2 70 , C o n tro l l er A re a N e two rk P h ysi ca l L aye r R e q u ire men ts , J a n u a ry 2 0 0 8 .

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