8051 interrupts

To serve several tasks or devices at a time by single microcontroller Conventional to polling: microcontroller continuously monitor the status of device/task, when the status condition is met, the microcontroller performs the service Interrupt: microcontroller interrupted by device/task causes execution of program associated with the interrupt called Interrupt Service Routine (ISR)

Advantages of interrupts:
Microcontroller can serve many devices/tasks Priority to the devices/tasks can assign Masking (ignoring) interrupt request of devices/tasks is possible Doesn t waste the time to check the status of devices/tasks

Interrupt Service Routine:

All interrupts must have ISR or interrupt handler There is a fixed location in code memory that holds the ISR Group of memory location addresses of ISRs is called Interrupt Vector Table

 Interrupt Vector Table of 8051

Interrupt Reset INT0 (External h/w interrupt 0) TF0(Timer 0 interrupt) INT1 (External h/w interrupt 1) TF1 (Timer 1 interrupt) RI and TI (Serial port interrupt) ROM location (ISR address) 0000H 0003H 000BH 0013H 001BH 0023H P3.3 (13) Pin RESET (9) P3.2 (12) Flag clearing Auto Auto Auto Auto Auto Programmer clears it

 Steps in executing an interrupt

Finishes the instruction executing and save the address of next instruction on the stack Saves the current status of all interrupts internally (not on stack) Jumps to fixed location in memory in IVT, that holds the address of ISR Starts execution of ISR until it reaches last instruction of subroutine, which must be RETI Returns to place where microcontroller is interrupted continue the process from saved address and status

8051 interrupt handling registers

IE (Interrupt Enable) Register
8-bit, bit addressable SFR byte address : A8H,

IP (Interrupt Priority) Register 8-bit, bit addressable SFR byte address: B8H,

Set to 1 cause high priority

 Interrupt priority
Highest to lowest priority External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port INT0 TF0 INT1 TF1 RI and TI

Programming timer interrupts

Steps:
Select timer by TMOD, load THx and TLx Enable timer interrupt by IE Run timer by TRx bit in TCON ISR of timer must contain the program for task Note: 1. Must avoid the memory space allocated to IVT for main program 2. If ISR is more size than allocated space (000BH-0003H = 0008H, maximum 8 bytes), use jump instructions to point somewhere else in program memory

 Program to generate square wave of 3kHz using timer 1 interrupt (12MHz Xtal frequency)
ORG 0 LJMP MAIN ORG 001BH ISR_T1:CPL P1.7 RETI ORG 0030H MAIN: MOV TMOD,#00100000B MOV TH1,#5AH MOV TL1,TH1 MOV IE,#10001000B SETB TR1 WAIT: SJMP WAIT END

; TIMER 1, MODE 2, AUTO RELOAD ; COUNT VALUE FOR 0.1666mS ; EA =1 and ET1 = 1

 Program to generate a square pulse of 6kHz at pin P1.6 and a rectangular pulse of 5kHz, 25% duty cycle at pin P1.7
ORG 0 LJMP MAIN ORG 000BH CPL P1.6 RETI ORG 001BH ISR_T1:LJMP RECT_ISR ORG 0030H MAIN: MOV TMOD,#00100010B; TIMER 1 & , MODE 2- AUTO RELOAD MOV TH0,#0ADH ; COUNT VALUE FOR 83uS MOV TL0,TH0

WAIT:

MOV IE,#10001010B ; EI = 1, ET1 & ET0 = 1 SETB TR0 MOV TH1,#0D8H ; Count value for 50us MOV TL1,TH1 SETB TR1 SJMP WAIT

RECT_ISR: JNB P1.7,HIGH_PULSE LOW_PULSE: MOV TH1,#6AH ; Count value for 150us MOV TL1,TH1 CPL P1.7 RETI HIGH_PULSE: MOV TH1,# 0D8H ; Count value for 50us MOV TL1,TH1 CPL P1.7 RETI END

Programming external hardware interrupts

INT0 (P3.2) and INT1 (P3.3) Activating these interrupts, 8051 execution jumps to the ISRs of IVT location 0003H and 0013H respectively Enabled by IE register Two type triggering:
Level triggered Edge triggered

SFR to select triggering, TCON

Lower nibble
IEx : set to 1 by microcontroller when external interrupt edge (H to L) is detected, cleared by microcontroller when the interrupt is processed ITx : Interrupt type control bit, set to 1 specify falling edge triggering external interrupt, cleared specify low level triggered external interrupt

 Program for up/down counter and display the count. Switch SW1 on P3.2 for up count and SW2 on P3.3 for down count. Display is a seven segment display on port 1
ORG 0 LJMP MAIN ORG 0003H LJMP UP ORG 0013H LJMP DOWN

MAIN: MOV R1,#00 MOV DPTR,#LUT CONTINUE: CLR A ADD A,R1 MOVC A,@A+DPTR MOV P1,A MOV IE,#10000101B; EA = 1, EX1 = 1 & EX0 =1 SETB IT0 ; Edge triggering INT0 SETB IT1 ; Edge triggering INT1 SJMP CONTINUE UP: INCR: CJNE R1,#09,INCR RETI INC R1 RETI

DOWN: DECR:

CJNE R1,#0,DECR RETI DEC R1 RETI

 Minimum duration for low level triggering signal is 4 Machine cycles Minimum pulse duration to detect edge triggered interrupt is 1 Machine cycle HIGH and 1 Machine cycle LOW Difference between RET and RETI instructions
Both return to main program RETI clears ISR flags, indicates the service is over If RET is used all other lower priority interrupts are blocked