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FPGA design
with
Verilog
Literature
- Real World FPGA Design with Verilog by Ken Coffman, Prentice Hall PTR - On-line Verilog HDL Quick Reference Guide by Stuart Sutherland titan.etf.bg.ac.yu/~gvozden/VLSI/
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Field Programmable Gate Array design Verilog designed as a simulation and test language Real World - &!!! #$%&@#$%
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Understandable Design
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FPGA Architecture
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Solution:
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Simulation
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Assignments
Concurrent Initial: A=B=C=E=1 A <= B + C; D <= A + E; After assignment: A=2, D=2 Milo Milovanovi Sequential Initial: A=B=C=E=1 A = B + C; D = A + E; After assignment: A=2, D=3
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Module
module module_name (port_name, port_name, ... ); module_items endmodule module module_name (.port_name (signal_name ), .port_name (signal_name ), ... ); module_items Milo Milovanovi 16 /75 endmodule
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Assign statement
Continuous (combinational) logic - net_type [size] net_name;
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Procedural Blocks
type_of_block @(sensitivity_list) statement_group: group_name local_variable_declarations timing_control procedural_statements end_of_statement_group
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Type of block
initial always process statements one time process statements repeatedly
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Sensitivity list
OPTIONAL Signals Posedge rising-edge triggered Negedge falling-edge triggered example: always @ (posedge clk or posedge rst) begin end
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Statement group
begin end the sequential block
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Example
initial fork #10 bus = 16'h0000; #20 bus = 16'hC5A5; #30 bus = 16'hFFAA; join
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Example
always begin #10 bus = 16'h0000; #20 bus = 16'hC5A5; #30 bus = 16'hFFAA; end
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Example
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Verilog Hierarchy
module_name instance_name(port_list);
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Basic Latch
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test_out2 <= 0;
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Nonblocking Assignment
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default: 32 bits wide size base value underscore is legal X is undefined Z is the high impedance
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Number examples
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Forms of Negation
! logical negation
~ - bitwise negation
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Forms of AND
& is a bitwise AND && is a logical AND (true/false)
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Forms of OR
| is a bitwise OR || is a logical OR (true/false)
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AND/OR examlpe
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Equality Operators
== is logical equality have an unknown (x) result if any of the compared bits are x or z === is case equality looks for exact match of bits including x s and z s and return only true or false
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Also supported
greater than (>) less than (<) greater than or equal (>=) less than or equal (<=)
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Shift operators
>> n << n right shift (divide by 2n) left shift (multiple by 2n)
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Conditional Operator
out <= expression ? true_assignment : false_assignment;
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Math Operators
addition (+), subtraction (-), multiplication (*), division (/), modulus (%) synthesis tool probably limits multiplication and division to constant powers of two verilog assumes all reg and wire variables are unsigned
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Parameters
used in modules where they are defined can be changed by higher-level modules cannot be changed at run time
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Concatenations
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Programming Statements
if, case casez, casex forever, repeat(number), while, for initial begin clk = 0; #1000 forever #25 clk = ~clk; end
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Testing
Compiler directives:
define, ifdef, else, endif, undef include timescale unit/precision example: timescale 1ns/0.5ns
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System Tasks
starts with $ $finish $stop terminate (time out)
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System Tasks
$display(format, vars ) - printf $write(format, vars ) - $display + \n $timeformat $time
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System Tasks
$monitor (signal list and formatting) $monitoron $monitoroff
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System Tasks
$dumpfile( filename ) $dumpvars $dumpall $dumpvars( ) $dumplimit(size)
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System Tasks
$readmemh( filename , memory_name) $readmemb( filename , memory_name)
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Real World
FPGA design
with
Verilog