Future of Nano CMOS Technology

International Workshop on The Future of Nano Electronics Research and Challenges Ahead

December 26, 2011

Hiroshi Iwai, Tokyo Institute of Technology

Tokyo Institute of Technology Founded in 1881, Promoted to Univ. 1929

International Students
Europe 78 North America 12

Africa 16

Asia 847
Oceania 5

Country China S. Korea Indonesia Thailand Vietnam Malaysia

Students 403 130 64 55 60 28

South America 24

Total 982
(As of May. 1, 2005)

Electronic Circuits started by the invention of vacuum tube (Triode) in 1906

Thermal electrons from cathode controlled by grid bias
Lee De Forest

Cathode (heated)

Grid

Anode (Positive bias)

Same mechanism as that of transistor

st Computer Eniac: made of huge number of vacuum tubes 19 Big size, huge power, short life time filament

dreamed of replacing vacuum tube with solid-state device Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption

J. E. LILIENFELD
DEVICES FOR CONTROLLED ELECTRIC CURRENT

Filed March 28, 1928

J.E.LILIENFELD

Capacitor structure with notch

Negative bias

Gate Electrode Gate Insulator Semiconductor

No current

Electron

Positive bias

Electric field
10

Current flows

Mechanism of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) G Surface Gate electrode
Gate Oxd Channel

Source

Drain

S Electron flow

0 bias for gate Surface Potential (Negative direction)

Positive bias for gate

0V N+-Si

Negative P-Si 1V N-Si Drain

0V N+-Si Source P-Si Channel

Source

Channel

1V N-Si Drain

However, no one could realize MOSFET operation for more than 30 years. Because of very bad interface property between the semiconductor and gate insulator Even Shockley!

12

Very bad interface property between the semiconductor and gate insulator Interfacial Charges

GeO Ge
e

Electric Shielding

Carrier Scattering

n Current was several orders of magnitude sm expected

Even Shockley!

13

However, they found amplification phenomenon when investigating Ge surface when putting needles. This is the 1st Transistor: Not Field Effect Transistor, But Bipolar Transistor (another mechanism)

1947: 1st transistor

J. Bardeen

W. Bratten,

Bipolar using Ge

W. Shockley

14

1960: First MOSFET by D. Kahng and M. Atalla

Top View

Si e rc ou S in ra D Si

te a lG A
Al SiO2 Si Si/SiO2
Interface is 15 exceptionally

1970,71: 1st generation of LSIs

1kbit DRAM Intel 1103

4bit MPU

Intel 4004

16

2011 Most recent SD Card

17

Most Recent SD Card 128GB (Bite) = 128G X 8bit = 1024Gbit = 1.024T(Tera)bit

1T = 1012 = Trillion
World Population 7 Billion Brain Cell 10 100 Billion Stars in Galaxy 100 Billion
18

Most Recent SD Card

19

2.4cm X 3.2cm X 0.21cm Volume 1. 6cm Weight 2g Voltage 2.7 - 3.6V Old Vacuum Tube 5cm X 5cm X 10cm, 100g,100W 1Tbit = 10k X10k X 10k bit Volume = 0.5km X 0.5km X 1km = 0.25 km3 = 0.25X1012cm3 Weight = 0.1 kgX1012 = 0.1X109ton = 100 M ton Power = 0.1kWX1012=50 TW Supply Capability of Tokyo Electric Power Company: 55 BW
20

So, progress of IC technology is most important for the power saving!

Downsizing of the components has been the driving force for circuit evolution
1900 1950 1960 1970 LSI 10 m 10-5m 2000 ULSI 100 nm 10-7m Vacuum Transistor IC Tube 10 cm cm mm 10 m
-1

10 m
-2

10-3m

In 100 years, the size reduced by one million times. There have been many devices from stone age. We have never experienced such a tremendous reduction of devices in human history.

22

nsizing Reduce Capacitance Reduce switching time of MOSFETs Increase clock frequency Increase circuit operation speed Increase number of Transistors Parallel processing Increase circuit operation speed
Downsizing contribute to the performance increase in double ways

hus, downsizing of Si devices is e most important and critical iss

23

Question: How far we can go with downscaling?

Many people wanted to say about the limit. Past predictions were not correct!! Expected Period Cause
limit(size)

Late 1970s 1m: Early 1980s 0.5m: arly 1980s 0.25m: ate 1980s 0.1m: 50nm: 10nm:

SCE S/D resistance Direct-tunneling of gate S 0.1m brick wall(various Fundamental?

25

2000

Red brick wall (various)

000

Historically, many predictions of the limit of downsizing. VLSI text book written 1979 predict that 0.25 micro-meter would be the limit

because of direct-tunneling current through the very thin-gate oxide.

VLSI textbook
Finally, there appears to be a 10 fundamental limit of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide ..... begin to make the devices of smaller dimension unworkable.
27

Direct-tunneling effect
Gate Oxide Si Gate Substrate Electrode Potential Barrier
Wave function Direct tunneling current
G Gate Oxide

Direct tunneling leakage current start to flow when 28 the thickness is 3 nm.

Gate electrode Gate oxide Si substrate

Lg G S D

MOSFETs with 1.5 nm gate oxide Lg = 10 m

0.03 Vg = 2.0V 0.08

Direct tunneling leakage w found to be OK! In 1994!

Lg = 1.0 m
0.4 1.6

Lg = 5 m

Lg = 0.1m

Vg = 2.0V 0.02 1.5 V 0.01 1.0 V Id (mA / m) 0.00 0.5 V 0.01 0.00 0.02 0.5 V 0.0 V 0.0 0.04 1.0 V 0.1 0.06 1.5 V 0.2 0.3

Vg = 2.0V 1.2 1.5 V 0.8 1.0 V 0.4 0.5 V 0.0

Vg = 2.0V

1.5 V 1.0 V

0.5 V

0.0 V

0.0 V

0.0 V

-0.4 0.0 0.5 1.0

-0.02 0.0 1.5

-0.1 0.5 1.0 1.5 0.0 0.5 1.0 1.5

-0.4 0.0 0.5 1.0 1.5

Vd (V)

Vd (V)

Vd (V)

Vd (V)

29

G S D

Gate leakage: Ig Gate Area Gate length (Lg) Drain current: Id 1/Gate length (Lg) Lg small, Then, Ig small, Id large,
Lg = 10 m
0.03 Vg = 2.0V 0.08

Ig Id

Thus, Ig/Id very small

Lg = 1.0 m
0.4 1.6 Vg = 2.0V 0.3 1.5 V 1.5 V 0.2 1.0 V 1.0 V 0.1 0.5 V 0.5 V 0.0 0.0 V 0.0 V 0.0 0.0 V 0.4 0.5 V 0.8 1.0 V 1.2 1.5 V

Lg = 5 m
Vg = 2.0V

Lg = 0.1m
Vg = 2.0V

Id
Id (mA / m)

0.02 1.5 V 0.01 1.0 V 0.00 0.5 V 0.01 0.0 V

0.06

0.04

0.02

0.00

-0.4 0.0 0.5 1.0 1.5

-0.02 0.0 0.5 1.0 1.5

-0.1 0.0 0.5 1.0 1.5

-0.4 0.0 0.5 1.0 1.5

30

Vd (V)

Vd (V)

Vd (V)

Vd (V)

Do not believe a text book statement, blindly!

Never Give Up! No one knows future! There would be a solution! Think, Think, and Think! Or, Wait the time! Some one will think for you
31

Qi Xinag, ECS 2004,32 AMD

So, what is the limitation for downsizing?

Surface

Gate electrode Gate Oxd Channel

Source

Drain

0 bias for gate Surface Potential (Negative direction)

0V N+-Si

Negative P-Si

Tunneling

3nm
Source Channel

1V N-Si Drain

@Vg=0V, Transistor cannot be switched off

34

Prediction now!
Limitation for MOSFET operation

Tunneling distance 3 nm

Lg = Sub-3 nm?
Below this, no one knows future!

How far can we go for production?

Past
1970 0.35m 0.25m 180nm 130nm 90nm 65nm 45nm 32nm

In 40 years: 18 generations, Now 0.7 times per 3 years Size 1/300, Area 1/100,000

10m 8m 6m 4m 3m 2m 1.2m 0.8m 0.5m

Future

(28nm) 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm?

ever, oxide thickness is now around 1nm

.8 nm: 2 mono-layer thickness!!

By Robert Chau, IWGI 200

37

So, we are now Facing the limit of downsizing?

38

K: There is a solution! Dielectric Constant To use high-k dielectrics

Thin gate SiO2

Thick gate high-k dielectric

Physical ly thick Same electric al

K=4 Almost the same

electric characteristics K=20

However, very difficult and big challenge! Remember MOSFET had not been realized without Si/SiO2!
39

5 nm gate length CMOS

Is a Real Nano Device!!
5 nm

ength of 18 Si atoms

H. Wakabayashi et.al, NEC IEDM, 2003

40

So, again, how far we can go with downscaling?

How far can we go for production?

Past
1970 0.35m 0.25m 180nm 130nm 90nm 65nm 45nm 32nm

In 40 years: 18 generations, Now 0.7 times per 3 years Size 1/300, Area 1/100,000

10m 8m 6m 4m 3m 2m 1.2m 0.8m 0.5m

Future

(28nm) 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm? At least 4,5 generations to 8nm Hopefully 8 generations to 3nm

Subtheshold leakage current of MOSFET

Id Ion
OFF ON

Subthreshould Leakage Current Ioff Vg=0V Subthreshold region Vth (Threshold Voltage) Vg

43

Vth cannot be decreased anymore

Log Id per unit gate width (= 1 m)
Ion

Log scale Id plot

10-3A 10-4A 10-5A 10-6A 10-7A 10-8A 10-9A 10-10A Vdd=0.5V Vdd=1.5V Vth down-scaling Vth = 300mV Vth = 100mV Vg = 0V Vg (V) Vdd down-scaling

significant Ioff increase

Ioff

Vth: 300mV 100mV Ioff increases with 3.3 decades

(300 100)mV/(60mv/dec) Ioff = 3.3 dec

Subthreshold slope (SS) = (Ln10)(kT/q)(Cox+CD+Cit)/Cox > ~ 60 mV/decade at RT

SS value: Constant and does not become small with down-scaling

44

44

Subtheshold leakage current of MOSFET

Id Ion
OFF ON

Subthreshold Current Is OK at Single Tr. level But not OK For Billions of Trs.

Subthreshould Leakage Current Ioff Vg=0V Subthreshold region

Vg Vth (Threshold Voltage)

45

The limit is deferent depending on application

100 e)

Operation Frequency (a.u.)

10

Subthreshold Leakage (A/m)

Source: 2007 ITRS Winter Public Conf.
46

The down scaling of MOSFETs is still possible for at least another 10 years! 3 important technological items for down scaling. New materials 1. Thinning of high-k gate oxide thickness beyond 0.5 nm 2. Metal S/D New structures 3. Wire channel

1. High-k beyond 0.5 nm

Choice of High-k elements for oxide

Candidates
Si + MOX M + SiO2 L B Si + MO MSi + SiO X X 2 e Si + MO M + MSi O i Mg X X Y Na
H

Gas or liquid at 1000 K

Unstable at Si interface

Radio B C N

Al Si P S Cl Ar Br I At

HfO2 based dielectrics are selected as the active first generation He materials, because of their merit in O F Ne 1) band-offset, 2) dielectric constant 3) thermal stability

Ca Sc Cr MnFc Co Ni Cu Zn Ga Ge As Se K Ti V Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te Rh Hf Cs Ba Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po Fr Ra Rf Ha Sg Ns Hs Mt

Kr Xe Rn

LaCePrNdPm EuGdTbDyHoErTmY Lu Sm

La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer

Ac Th Pa U Np Pu AmCmBk Cf Es FmMdNo Lr

R. Hauser, IEDM Short Course, 1999 Hubbard and Schlom, J Mater Res 11 2757 (1996)

49

Conduction band offset vs. Dielectric Constan

Leakage Current by Tunneling B a n d D is c o n t in u it y [e V ]
Oxide

i2O

4 2 0 - 2 - 4 - 6 0 1 0 2 0 3 0 4 0 5 0 D i e l e c t r i c C o n s t a n t
XPS measurement by Prof. T. Hattori, INFOS 2003
50

Band offset

High-k gate insulator MOSFETs for Intel: EOT=1nm HfO2 based high-k
PMOS

51

(S ca l

in g

For the past 45 years SiO2 and SiON For gate insulator

Metal
SiO2/SiON

Metal
HfO2 SiO2/SiON

Power per MOSFET (P)

Si

0.5 0.7nm

Lg

Today EOT=1.0nm EOT Limit 0.7~0.8 nm One order of Magnitude EOT=0.5nm

EOT can be reduced further beyond 0.5 nm by using direct contact to Si By choosing appropriate materials and processes.

3
45nm node

Si Introduction of High-k

Still SiO2 or SiON Is used at Si interface

Metal
High-k

Si Direct Contact Of high-k and Si

Now

Year

52

Cluster tool for high-k thin film deposition

Sputter for metal 5 different target Preparation Room E-Beam Evaporation 8 different target Flash Lamp Anneal Robot Micro to mille-seconds room

SiOx-IL growth at HfO2/Si Interface

TEM image 500 oC 30min

Intensity (a.u)

XPS Si1s spectrum

500 oC SiO2 Hf Silicate Si sub.

W HfO2k=16 SiOx-IL

1846

1843

1840

1837

k=4

Binding energy (eV)

1 nm

Phase separator

HfO2 + Si + O2 HfO2 + Si + 2O*HfO2+SiO2

Oxygen supplied from W gate electrode

H. Shimizu, JJAP, 44, pp. 6131

SiOx-IL is formed after annealing 54 Oxygen control is required for optimizing the reaction

D.J.Lichtenwalner, Tans. ECS 11, 319

La-Silicate Reaction at La2O3/Si Direct contact high-k/Si is possible

XPS Si1s spectra
as depo. La-silicate Si sub.

TEM image 500 oC, 30 min

W La2O3

Intensity (a.u)

300 oC

k=23

La-silicate
500 oC

k=8~14

1 nm
1843 1840 1837

La2O3 + Si + nO2 Binding energy (eV) La2SiO5, La2Si2O7, La9.33Si6O26, La10(SiO4)6O3, 55 etc. La2O3 can achieve direct contact of high-k/Si
1846

Gate Leakage vs EOT, (Vg=|1|V)

1.E+01 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 0 0.5 1 1.5 EOT ( nm ) 2 2.5 3
Al2O3

HfO2

HfAlO(N) HfO2 HfSiO(N) HfTaO

Current density ( A/cm

La2O3

La2O3 Nd2O3 Pr2O3 PrSiO PrTiO SiON/SiN Sm2O3 SrTiO3 Ta2O5 TiO2 ZrO2(N) ZrSiO ZrAlO(N)
56

La2O3 at 300oC process make sub-0.4 nm EOT MOSFET

EOT=0.37nm
EOT=0.37nm
3.5E-03 3.0E-03

EOT=0.40nm
3.5E-03

EOT=0.48nm
3.5E-03

W/L = 50m /2.5m

Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V

W/L = 50m /2.5m

Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V

W/L = 50m /2.5m

Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V

Vth=-0.06V3.0E-03
2.5E-03 2.0E-03 1.5E-03 1.0E-03 5.0E-04 0.0E+00

Vth=-0.05V 3.0E-03
2.5E-03 2.0E-03 1.5E-03 1.0E-03 5.0E-04 0.0E+00 0.8 10

Vth=-0.04V

Id (V)

2.5E-03 2.0E-03 1.5E-03 1.0E-03 5.0E-04

0.0E+00 0 0.2 0.4 0.6

0.8

10

0.2

0.4

0.6

0.2

0.4

0.6

0.8

Vd (V)

Vd (V)

Vd (V)

0.48 0.37nm Increase of Id at 30%

57

However, high-temperature anneal is necessary for the good interfacial property FGA500oC 30min
2

FGA700oC 30min
1.5

FGA800oC 30min
2

20 x 20m

20 x 20m

20 x 20m

Capacitance [F/cm ]

Capacitance [F/cm ]

1.5

Capacitance [F/cm ]

10kHz 100kHz 1MHz

10kHz 100kHz 1MHz

1.5

10kHz 100kHz 1MHz

0.5

0.5

0.5

0 -1

-0.5 0 0.5 Gate Voltage [V]

0 -1.5

-1 -0.5 0 Gate Voltage [V]

0.5

0 -1.5

-1 -0.5 0 Gate Voltage [V]

0.5

A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC)
58

Physical mechanisms for small Dit

silicate-reaction-formed fresh interface stress relaxation at interface by glass type structure of La silicate.

metal La2O3
Si Si

metal La-silicate

La atom La-O-Si bonding SiO4 tetrahedron network

Si sub.

Si sub.

Si sub.

Fresh interface with silicate reaction

J. S. Jur, et al., Appl. Phys. Lett., Vol. 87, No. 10, (2007) p. 102908

FGA800oC is necessary to reduce the interfacial stress

S. D. Kosowsky, et al., Appl. Phys. Lett., 59 Vol. 70, No. 23, (1997) pp. 3119

Pulse input
500

Electron Mobility [cm /Vsec]

Charge pumping current [A]

10

-6

Dit = 2 x 1012 [cm-2/eV] 500oC Dit = 5 x 1011 [cm-2/eV] 700oC

400 300 200

FGA 800 C o FGA 700 C FGA 500 C

o

Universal

10

-7

10

-8

EOT~1.3nm
100 0 0

10

-9

800oC D = 1.6 x 1011 [cm-2/eV] it

10
4

T = 300K 16 -3 Nsub = 3 x 10 cm
0.2 0.4 0.6 Eeff [MV/cm] 0.8 1

10 Frequency [Hz]

10

A small Dit of 1.6x1011 cm-2/eV, results in better electron mobility.

60

EOT growth suppression by Si coverage

Si

Gate-Channel Capacitance [F/cm ]

FGA 800 C 30min

3

EOT=0.71nm

TiN W La-silicate Si sub.

10 10 10

-3 -4 -5 -6 -7 -8 -9

EOT=1.02nm

Drain Current [A]

L / W = 20 / 20m

Vds = 0.05V

TiN W La-silicate Si sub.

10 10 10 10 10 10 10

EOT=1.63nm

65~70mV/dec
EOT = 0.71nm EOT = 1.02nm EOT = 1.63nm L / W = 2.5 / 50m
-1 -0.5 0 Vg - Vth [V] 0.5 1

W La-silicate

-10 -11 -12

at 1MHz
0 -1 -0.5 0 0.5 Gate Voltage [V] 1

Si sub.

Increasing EOT caused by high temperature annealing can be dramatically suppressed by Silicon masked stacks
61

La2O3
W
MG HK

TiN/W

Si/TiN/W MIPS

Si

2nm

2nm

2nm

Kav ~ 8

Kav ~ 12

Kav ~ 16

No interfacial layer can be confirmed with Si/TiN/W

62

nMOSFET with EOT of 0.62nm

Gate-Channel Capacitance [F/cm ]
2

FGA 800 C 30min L / W = 10 / 10m

3

200

Electron Mobility [cm /Vsec]

10kHz 100kHz 1MHz

150

EOT=0.62nm

100

EOT=0.62nm
T = 300K 16 -3 Nsub = 3 x 10 cm L / W = 10 / 10m

No frequency dispersion

50

-0.5

0 0.5 Gate Voltage [V]

0.5

1 Eeff [MV/cm]

1.5

EOT of 0.62nm and 155 cm2/Vsec at 1MV/cm can be achieved

63

Benchmark of La-silicate dielectrics

T. Ando et al., IEDM2009

10 10

300

Electron Mobility [cm /Vsec]

ITRS requirements

at 1MV/cm
250 200 150 100 50

Jg at Vg = 1V [A/cm ]

10 10 10

This work (MIPS Stacks)

T = 300K

10 10

-1

MIPS Stacks
A = 10 x 10m
0.55 0.6 0.65 0.7 EOT [nm] 0.75
2

Open : Hf-based oxides

1.1 1.2 1.3

-2

0.5

0.8

0 0.5 0.6 0.7 0.8 0.9 1 EOT [nm]

Gate leakage is two orders of magnitude lower than that of ITRS

Electron mobility is comparable to record mobility with Hf-based oxides

64

Metal (Silicide) S/D

(a)
Extreme scaling in MOSFET mask
Dopant Conc.

(b)
Hard

Lphy Gate
n+-Si

- Dopant abruptness at S/D - Vt and ION variation Drain - GIDL Source

(b)

Metal Schottky S/D junctions

Gate Source

Drain

n+-Si

y position Channel

Metal Conc.

Gate - Atomically abrupt junction - Lowering S/D resistances - Low temperature process fortal Me S/D
Metal

Lphy = Leff
Gate

Schottky Barrier FET is a strong Metal candidate for textremely scaled n Me al MOSFET

Metal Silicide

Metal Silicide

y position Channel D

Surface or interface control

Diffusion species: metal atom (Ni, Co) Rough interface at silicide/Si - Excess silicide formation - Different Bn presented at interface - Process temperature dependent composition Diffusion species: Si atom (Ti) Surface roughness increases - Line dependent resistivity change

Annealing: 650 oC Si(001) sub. Epitaxial NiSi2

O. Nakatsuka et al., Microelectron. Eng., 83, 2272 (2006).

Top view Line width of 0.1 m

H. Iwai et al., Microelectron. Eng., 60, 157 (2002).

67

Annealing: 500 oC Current density (A/cm2)

Unwanted leakage current

- Edge leakage current at periphery - Generation current due to defects in substrate
Variable leakage current in smaller contact

Vapp = -0.2V 10-2

Bn = ~0.57 eV

10-3 10 102 Length of a contact side (m)

Ni silicide/Si diodes

Specification for metal silicide S/D - Atomically flat interface with smooth surface - Suppressed leakage current - Stability of silicide phase and interface in a wide process temperature 68

Ni-silicide

Deposition of Ni film

Rough interface

Si substrate

Annealing

Si substrate

Deposition from NiSi2 source

Ni-silicide

No Si substrate consumption Flat interface

Si substrate

Annealing

Si substrate

Deposition of Ni-Si mixed films from NiSi2 source

- No consumption of Si atoms from substrate - No structural size effect in silicidation process - Stable in a wide process temperature range
69

SEM views of silicide/Si interfaces

Ni source (50nm) NiSi2 source (50nm)
Ni source Ni-silicide NiSi2 source Ni-silicide STI Si substrate Si substrate

STI

rough

500nm

flat

STI 600oC , 1min

500nm

Ni source
STI rough
500nm

STI 700oC , 1min

flat

500nm

- Rough interfaces - Consumed Si substrate - Thickness increase ~100 nm

NiSi2 source
STI rough
500nm

flat

STI 800oC , 1min

500nm

- Atomically flat interfaces - No Si consumption - Temperature-independent

70

Ni source

Diode density (A/cm ) Currentcurrent (A/cm22)

10-2

RTA oC, 1min 500 Source Bn (eV) Ni 0.676 0.659 NiSi2 Ni n 1.08 1.00

Si substrate Al contact

10-3

NiSi2 source
Si substrate Al contact Schottky diode structures

Leakage current Generation current

10-4 NiSi2 10-5 -0.8 -0.6 -0.4 -0.2 0.0 Applied Voltage (V) Diode voltage (V) 0.2

NiSi2 source

Ideal characteristics (n = 1.00, suppressed leakage current)

Suppressed reverse leakage current - Flat interface and No Si substrate consumption - No defects in Si substrate

71

Wire channel

Suppression of subthreshold leakage by surrounding gate structure

0V 0V S 0V V 1V 0V G 1V 0V G 0V 1V D

0V

0V

Planar

Surrounding gate

73

Because of off-leakage control, Planar Nanowire 1

S D
1 V S 1 V 1 V G 1 V D G

W dep
Leakage current

1 V

Gate Source Drain

Planar FET

Fin FET

Nanowire FET

Nanowire structures in a wide meaning

G G G G

G
Fin Tri-gate -gate All-around 75

Si nanowire FET as a strong candidate 1. Compatibility with current CMOS process 2. Good controllability of IOFF

1
D

W dep
Leakage current

Off cut-off

Source drain

3. High drive current

Drain source

Gate:OFF Gate: OFF

1D ballistic conduction

Multi quantum Channel

Quantum channel Quantum channel Quantum channel Quantum channel
k

High integration of wires

76

Increase the Number of quantum channels

By Prof. Shiraishi of Tsukuba univ. 4 channels can be used

Eg
Eg

Energy band of Bulk Si

Energy band of 3 x 3 Si wire

77

Device fabrication
( )
Si/Si0.8Ge0.2 superlattice epitaxy on SOI
SiN HM
SiN SiN SiGe SiGe Si Si SiGe SiGe Si Si SiGe SiGe Si Si BOX BOX BOX BOX BOX BOX

Anisotropic etching of these layers

Isotropic etching of SiGe

The NW diameter is controllable down to 5 nm by self limited oxidation.

Gate depositions Gate etching

HfO2 (3nm) TiN (10nm) Poly-Si (200nm)
Gate

Gate

S/D implantation Spacer formation Activation anneal Salicidation Process Details :

Standard Back-End of-Line Process

C. Dupre et al., IEDM Tech. Dig., p.749, 2008

BOX BOX

3D-stacked Si NWs with Hi-k/MG

Top view
Source

Cross-section SiN HM
Drain Gate

500 nm

<110> NWs 50nm

BOX

Wire direction : <110> 50 NWs in parallel 3 levels vertically-stacked Total array of 150 wires EOT ~2.6 nm
C. Dupre et al., IEDM Tech. Dig., p.749, 2008

SiNW FET Fabrication

S/D & Fin Patterning
30nm

Sacrificial Oxidation Oixde etch back

30nm

SiN sidewall support formation

30nm

Gate Oxidation & Poly-Si Deposition Gate Lithography & RIE Etching Gate Sidewall Formation Ni SALISIDE Process (Ni 9nm / TiN 10nm) Backend Standard recipe for gate stack formation

Recent results to be presented by ESSDERC 2010 next week in Sevile Wire cross-section: 20 nm X 10 nm

Drain Current (A)

60

6.E-05

5.E-05 50 4.E-05 40 3.E-05 30

0.8 V 0.6 V Vg-Vth= -1.0 V 0.4 V 0.2 V

Drain Current (A)

7.E-05 70

(a)

Vg-Vth=1.0 V

1.E-03 10-3 1.E-04 10-4 1.E-05 10-5

(b) Vd=-1V

Vd=1V Vd=50mV nFET

1.E-06 10-6 V =-50mV d 1.E-07 -7 10 1.E-08 pFET 10-8 1.E-09 10-9

20 0

2.E-05

1.E-05 10 0.E+00

1.E-10 10-10 1.E-11 10-11 1.E-12 10-12

-1.0 -0.5 0.0

Drain Voltage (V)

0.5

1.0

-1.5 -1.0 -0.5 0.0 0.5 1.0

Gate Voltage (V)

Lg=65nm, Tox=3nm

On/Off>106 60uA/wire

Bench Mark
102A (10x20)
nMOS pMOS

VDD: 1.0~1.5 V
(12x19) (13x20)

Our Work

ION (A / wire)

(12) (12)

(10) (10) (8) (8)

(9x14)

70 60 50
(5) (10) (10) (3) (3) (30) (19)

(16) (34) (13)

(12x19) (5) (12) (10)

40 30

Gate Length 20 (nm) 10

ION/IOFF Bench mark

Planer FET 1.0 1.1V

S. Kamiyama, IEDM 2009, p. 431 P. Packan, IEDM 2009, p.659

hi T
Lg=500 65nm

k or w

1.2 1.3V Si nanowireFET Y. Jiang, VLSI 2008, p.34 H.-S. Wong, VLSI 2009, p.92 S. Bangsaruntip, IEDM 2009, p.297 C. Dupre, IEDM 2008, p. 749 S.D.Suk, IEDM 2005, p.735 G.Bidel, VLSI 2009, p.240

(x1019cm-3) 6 Edge portion 5

Electron Density

4 3 2 1 0
D istance fromS WS iN urface (nm )

Flat portion

Primitive estimation !
Compact model
12000 10000 8000 6000 4000

EOT Small EOT for high-k (33) pMOS P-MOS improvement (26)
Low S/D resistance S/D

SiNW (12nm 19nm)

ION (A/m)

(20) (15) (11)

1m/1m # of wires

Na no wi re

Assumption ION

IONLg-0.5 Tox-1 MG

2000 0 2008

bulk
2012 2014

FD

ITRS
2018 2020 2022

2010

2016

Year

2024

2026

Our roadmap for R &D

Source: H. Iwai, IWJT 2008

Current Issues Si Nanowire Control of wire surface property Source Drain contact Optimization of wire diameter Compact I-V model III-V & Ge Nanowire High-k gate insulator Wire formation technique CNT: Growth and integration of CNT Width and Chirality control
Chirality determines conduction types: metal or semiconductor

Graphene: Graphene formation technique Suppression of off-current Very small bandgap or no bandgap (semi-metal) Control of ribbon edge structure which affects bandgap 87

Thank you for your attention!

88