Microprocessor Slides-2

Dr. Ritika Department of Computer Application

8085 MPU
MPU is device or group of device(as a unit) that communicate with peripherals provide timing signals, direct data flow, and perform computing task as specified by the instructions in memory. 8085 is MPU but with 2 limitations: Low order address bus is multiplexed (time-shared) with data bus. The buses need to be demultiplexed. Appropriate control signals need to be generated to interface memory and I/O with the 8085.

Tri-State Devices
Interfacing Device necessary to interconnect the components of bus-oriented system. Devices essential for proper functioning of bus-oriented system. have 3 states : logic 1, logic 0, and high impedance. Trademark of National Semiconductor.

It is a useful device that allows us to control when current passes through the device, and when it doesn't.
Third line is called Enable is activated, tri-state device function same as ordinary logic device.

Tri-State Devices
When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into a high impedance state.

8085 MPU
8085 is 8-bit general purpose microprocessor. Capable of addressing 64K (216 = 65,536 registers ) of memory. 40 pin DIP(Dual in line package). +5V 3 - 5MHz
ADDRESS BUS DATA BUS CONTROL STATUS POWER SUPPLY AND FREQUENCY EXTERNALLY INITIATED SIGNALS SERIAL I/O PORTS

8085 Microprocessor Pinout and Signals

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8085 Microprocessor Pinout and Signals

8085 Microprocessor Pinout and Signals

Address Bus: A8 - A15 (output; 3-state) It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address; Multiplexed Address / Data Bus: AD0 - AD7 (input/output; 3-state) These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus. During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order address A0 - A7. In the subsequent IO / memory, read / write clock cycle the lines are used as data bus. The CPU may read or write out data through these lines.

8085 Microprocessor Pinout and Signals

Control and Status signals: ALE (output) - Address Latch Enable. This signal helps to capture the lower order address presented on the multiplexed address / data bus. RD (active low) - Read memory or IO device. This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device. WR (active low) - Write memory or IO device. This indicates that the data on the data bus is to be written into the selected memory location or I/O device. (output) - Select memory or an IO device. T his status signal indicates that the read / write operation relates to whether the memory or I/O device. It goes high to indicate an I/O operation. It goes low for memory operations. S1 and S0: These status signals, similar to , can identify various operations, but they are rarely used in small systems.

8085 Microprocessor Pinout and Signals

All the operations and their associated status signals are listed in Table for reference :

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Generating Control Signals

Four Control Signals are generated by combining the signals RD, WR and IO/M This signal is ANDed with RD and WR signals by using 74LS32 quadruple two input OR gates. OR gates are functionally connected as negative NAND gates.

When both inputs are low output are low generate MEMR and MEMW control signal.
IO/M goes high, indicates peripheral I/O operation.

Fig shows signal is complemented with hex inverter 74LS04 and ADDed with RD and WR signals to generate IOR and IOW control signals.

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8085 Microprocessor Pinout and Signals:

Power Supply And Clock Frequency
The power supply and frequency signals as follows: Vcc: +5V power supply. Vss: Ground Reference.

X1, X2: A crystal (or RC, LC network) is connected at these two pins. The frequency is internally divided by two; therefore, to operate a system at 3 MHz, the crystal should have a frequency of 6 MHz. CLK (OUT) Clock Output: This signal can be used as the system clock for other devices.

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8085 Microprocessor Pinout and Signals

Externally Initiated Signals, Including Interrupts The 8085 have five interrupt signals that can be used to interrupt a program execution. One of the signals, INTR (Interrupt Request), is identical to the 8080A microprocessor or interrupt signal (INT); the others are enhancement to the 8080A. The microprocessor acknowledges an interrupt request by the INTA (Interrupt Acknowledge) signal.

In addition to the interrupts, three pinsRESET, HOLD and READY accept the externally initiated signals as inputs. To respond to the HOLD request, it has one signal called HLDA (Hold Acknowledge).
RESET IN: When the signal on this pin goes low, the program counter is set to zero, the buses are tri-stated, and the MPU is reset. RESET OUT: This signal indicates that the MPU is being reset. This signal can be used to reset other devices
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8085 Microprocessor Pinout and Signals

Serial I/O Ports The 8085 have two signals to implement the serial transmission: SID (Serial Input Data) and SOD (Serial Output Data).

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FUNCTIONAL BLOCK DIAGRAM OF 8085

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TIMING DIAGRAM
Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in Tstates. Instruction Cycle: The time required to execute an instruction is called instruction cycle. 8085 instruction cycle consist of 1 to 6 machine cycle ( or operations). Machine Cycle: The time required to complete one operation of accessing memory, input/output devices or acknowledging an external request is called machine cycle. It consist of 3 to 6 T-states. T-State ( or Clock Period): The machine cycle and instruction cycle takes multiple clock periods. A portion of an operation carried out in one system clock period is called as Tstate. These subdivision are internal states synchronized by system clock.
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MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 basic machine cycles. They are:

Opcode fetch cycle (4T) Memory read cycle (3 T) Memory write cycle (3 T) I/O read cycle (3 T) I/O write cycle (3 T)
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Microprocessor Communication and Bus Timings

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Microprocessor Communication and Bus Timings

Opcode fetch machine cycle of 8085 : Each instruction of the processor has one byte opcode. The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch the opcode from memory. Hence, every instruction starts with opcode fetch machine cycle. The time taken by the processor to execute the opcode fetch cycle is 4T. In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.
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Microprocessor Communication and Bus Timings

To understand the functions of various signals of the 8085, we should examine the process of communication (reading from and writing into the memory) between the microprocessor and memory and the timings of these signals in relation to the system clock. The first step in the communication process is reading from memory or fetching an instruction. Step 1: The microprocessor places the 16-bit memory address from the program counter (PC) on the address bus. At T1 20H is placed on A15-A8 and 05H is placed on AD7-AD0. ALE goes high, goes low. Step 2: The control unit sends the control signal RD to enable the memory chip. It is active during 2 clock periods. Step 3: The byte (4FH)from the memory location is placed on the data bus (AD7AD0) when memory is enabled and when RD goes high it causes buses to go into high impedance. Step 4: The byte (4FH) is placed in the instruction decoder of the microprocessor, and the task is carried out according to the instruction. 4FH (MOV C, A) is decoded and contents of the accumulator are copied into register C.
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Microprocessor Communication and Bus Timings

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Demultiplexing the Bus AD7-AD0

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Need for Demultiplexing the Bus AD7-AD0

Address on high-order bus (20H) remains on bus for three clock periods.

Low order address 05H is lost after the first clock period.
Address need to be latched and used for identifying memory location (2005H), the address will change to 204FH after first clock periods. when ALE goes high (during T1), the latch is transparent (output changes according to input). During T1 output of latch is 05H. When ALE goes Low, the data byte 05H is latched until next ALE, and output of latch represents the low-order address bus AD7-AD0 after latching operation.

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Memory Read Machine Cycle of 8085:

Memory Read Machine Cycle of 8085: The memory read machine cycle is executed by the processor to read a data byte from memory. The processor takes 3T states to execute this cycle. The instructions which have more than one byte word size (like MVI A,32H that is load byte 32H in the accumulator) will use the machine cycle after the opcode fetch machine cycle.

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Memory Read Machine Cycle of 8085

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Examining 2-byte instruction for memory Read

To examine Memory Read operation we always examine 2-byte or 3-byte instruction because in 1-byte instruction machine code is an opcode therefore operation is always an Opcode Fetch. To understand the memory read machine cycle, lets study the execution of the following instruction MVI A, 32 In memory, this instruction looks like: -The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A),
the second byte is the data to be loaded.

The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it will need at least two machine cycles.
-The first machine cycle is the opcode fetch discussed earlier. -The second machine cycle is the Memory Read Cycle.
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Need for Demultiplexing the Bus AD7-AD0

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I/O Write Cycle of 8085

The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a peripheral, which is I/O, mapped in the system. The processor takes, 3T states to execute this machine cycle. The 8085 instructions consist of one to five machine cycles. Actually the execution of an instruction is the execution of the machine cycles of that instruction in the predefined order. The timing diagram of an instruction ate obtained by drawing the timing diagrams of the machine cycles of that instruction, one by one in the order of execution.

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I/O Write Cycle of 8085

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