PENTIUM

CREATED BY:
Akanksha mahapatra

CONTENTS
Introduction

Architecture
Register

Sets Addressing Modes Operating Modes Instruction Sets Features Conclusion

INTRODUCTION
Based on P5 micro-architecture. Pentium is the first high-performance microprocessor to include a system management mode like those found on power-miserly processors for notebooks and other battery-based applications. fabricated in 0.8-micron bipolar complementary metal oxide semiconductor (BiCMOS) technology. Single +5.0V power supply operations Pentium uses about 3 million transistors Microprocessor of 4GB in size twice the performance of a Intel486 processor per clock cycle. Operates at 60MHZ and 66MHZ.

ARCHITECTURE

A Pentium processor's major functional components are:

Core: The heart of a Pentium is the execution unit. The Pentium has two parallel integer pipelines enabling it to read, interpret, execute and despatch two instructions simultaneously. Branch Predictor: The branch prediction unit tries to guess which sequence will be executed each time the program contains a conditional jump, so that the Prefetch and Decode Unit can get the instructions ready in advance. Floating Point Unit: The third execution unit in a Pentium, where non-integer calculations are performed. Level 1 Cache: The Pentium has two on-chip caches of 8KB each, one for code and one for data, which are far quicker than the larger external secondary cache. Bus Interface: brings a mixture of code and data into the CPU, separates the two ready for use, and then recombines them and sends them back out.

WHAT IS A REGISTER

The Registers are a ministorage area for data used by the Arithmetic Logic Unit (ALU) to complete the tasks the Control Unit has requested. The data can come from the data cache, main memory or the control unit and are all stored at special locations within the Registers. This makes retrieval for the ALU quick and efficient.

GENERAL PURPOSE REGISTERS

32-bit 16-bit 88-bit(low bit(high part of 16)
part of 16)

EAX(accumulator) AX
EBX(base) BX

AH
BH

AL
BL

ECX(counter)
EDX(data)

CX
DX

CH
DH

CL
DL

SEGMENT REGISTERS

EFLAGS REGISTERS

ADDRESSING MODES
effective

address = base reg + (index reg x scaling factor) + displacement where base reg is EAX, EBX, ECX, EDX or ESP or EBP; index reg is EDI or ESI; scaling factor is 1, 2, 4, or 8 .

ADDRESSING MODES

REGISTER MODE: The operand is in a register. The effective address is the register. Eg: MOV EAX,ECX Both operands use register mode. The contents of register ECX is copied to register EAX.

IMMEDIATE MODE :The operand is in the instruction. The effective address is within the instruction. Eg: MOV EAX, 26 The second operand uses immediate mode. Within the instruction is the operand. It is copied to register EAX.

ADDRESSING MODES

REGISTER DIRECT MODE : The effective address is in a register. Eg: MOV EAX, [ESP] The second operand uses register direct mode. The contents of register ESP is the effective address. The contents of memory at the effective address are copied into register EAX. DIRECT MODE :The Effective address is in the instruction. Eg: MOV EAX, var_name The second operand uses direct mode. The instruction contains the effective address. The contents of memory at the effective address are copied into register EAX.

ADDRESSING MODES

BASE DISPLACEMENT MODE :The effective address is the sum of a constant and the contents of a register. Eg: MOV EAX, [ESP + 4] The second operand uses base displacement mode. The instruction contains a constant. That constant is added to the contents of register ESP to form an effective address. The contents of memory at the effective address are copied into register EAX. BASE INDEXED MODE: The effective address is the sum of the contents of two registers. Eg: MOV EAX, [ESP][ESI] The contents of registers ESP and ESI are added to form an effective address. The contents of memory at the effective address are copied into register EAX.

OPERATING MODES

PROTECTED MODE: This is the native state of the microprocessor. In this mode all instructions and architectural features are available, providing the highest performance and capability. This is the recommended mode that all new applications and operating systems should target. Among the capabilities of protected mode is the ability to directly execute "real-address mode" 8086 software in a protected, multi-tasking environment. This feature is known as Virtual-8086 "mode" (or "V86 mode"). REAL-ADDRESS MODE: This mode provides the programming environment of the Intel 8086 processor, with a few extensions (such as the ability to break out of this mode). Reset initialization places the processor in real mode where, with a single instruction, it can switch to protected mode.

SYSTEM MANAGEMENT MODE

The Pentium microprocessor also provides support for System Management Mode (SMM). SMM is a standard architectural feature unique to all new Intel microprocessors, beginning with the Intel386 SL processor, which provides an operating-system and application independent and transparent mechanism to implement system power management and OEM differentiation features. SMM is entered through activation of an external interrupt pin (SMI#), which switches the CPU to a separate address space while saving the entire context of the CPU. SMM-specific code may then be executed transparently. The operation is reversed upon returning.

INSTRUCTION SETS

Instruction set is divided into 9 categories of operations and has 11 addressing modes. In addition to commonly available instructions in a 8 bit microprocessor and this set includes operations such as bit manipulation and string operations, high level language support and operating system support. An instruction may have 0-3 operands and the operand can be 8, 16, or 32- bits long. The 80386 handles various types of data such as Single bit , string of bits , signed and unsigned 8-, 16-, 32- and 64- bit data, ASCII character and BCD numbers. Integer Arithmetic Logical Arithmetic Floating Point Arithmetic I/O Control Instructions

 Many

of the instructions have exactly 2 operands. If there are 2 operands, then one of them will be required to use register mode, and the other will have no restrictions on its addressing mode. There are most often ways of specifying the same instruction for 8-, 16-, or 32-bit operands.

NEW INSTRUCTIONS IN PENTIUM

INSTRUCTION
CMPXHG8B CPUID RDTSC

FUNCTION
Compare and exchange 8-bytes Return CPU identification code Read time-stamp counter Read/Write modelspecific register Return from system management interrupt

RDMSR/WRMSR
RSM

FEATURES
The Pentium processor achieves higher performance than the fastest Intel486 processor by making use of the following advanced technologies. SUPERSCALAR EXECUTION: The Intel486 processor can execute only one instruction at a time. With superscalar execution, the Pentium processor can sometimes execute two instructions simultaneously.

PIPELINE ARCHITECTURE: Like the Intel486 processor, the Pentium processor executes instructions in five stages. This staging, or pipelining, allows the processor to overlap multiple instructions so that it takes less time to execute two instructions in a row. Because of its superscalar architecture, the Pentium processor has two independent processor pipelines.

FEATURES

INSTRUCTION OPTIMIZATION: The Pentium processor has been optimized to run critical instructions in fewer clock cycles than the Intel486 processor. FLOATING-POINT OPTIMIZATION: The Pentium processor executes individual instructions faster through execution pipelining, which allows multiple floating-point instructions to be executed at the same time.

PENTIUM EXTENSIONS: The Pentium processor has fewer instruction set extensions than the Intel486 processors. The Pentium processor also has a set of extensions for multiprocessor (MP) operation. This makes a computer with multiple Pentium processors possible.

CONCLUSION
High

heat production due to 5V operation Lack of multimedia applications. If for any reason the branch prediction logic errs, the branch requires an extra three clocking periods to execute. A Pentium system, with its wide, fast buses, advanced write-back cache/memory subsystem, and powerful processor, will deliver more power for today's software applications, and also optimize the performance of advanced 32-bit operating systems (such as Windows 95) and 32-bit software applications.

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