Clocking in digital systems

By Bhanu prasad nimmagadda Roll no 3

contents
Introduction Classification of Digital Systems Synchronous Design Synchronous Timing Basics Sources of Skew and Jitter Clock-Distribution Techniques Synchronizers and Arbiters Clock Synthesis and Synchronization Using a PhaseLocked Loop Mesochronous pipelining scheme

 All sequential circuits have one property in commona well-defined ordering of the switching events must be imposed if the circuit is to operate correctly. If this were not the case, wrong data might be written into the memory elements, resulting in a functional failure. The synchronous system ap proach, in which all memory elements in the system are simultaneously updated using a globally distributed periodic synchronization signal (that signals and their distribution to the memory elements distributed over the chip; non-compliance often leads to malfunction.

At the other end of the design spectrum is an approach called asynchronous design which avoids the problem of clock uncertainty alltogether by eliminating the need for globally-distributed clocks. After discussing the basics of asynchronous design approach

Synchronous Interconnect
CLK In R1 Combinational R2 Logic Cout Cin Out

Mesochronous interconnect

Plesiochronous Interconnect

Asynchronous Interconnect

Latch parametes
D Q Clk

T
PWm thold Q tc-q td-q tsu

Clock skew
The spatial variation in arrival time of a clock transition on an integrated circuit is commonly referred to as clock skew

Positive and Negative Skew

In CLK R1 D Q tCLK1 delay (a) Positive skew R1 D Q tCLK1 delay
(b) Negative skew Combinational Logic

R2 D Q tCLK2
delay Combinational Logic

R3
D Q

tCLK3

In

Combinational Logic

R2 D Q tCLK2 delay Combinational Logic

R3 D Q tCLK3 CLK

Positive Skew
TCLK + d CLK1 1
d

TCLK

CLK2

2
d + th

Launching edge arrives before the receiving edge

Negative Skew
TCLK + d

CLK1

TCLK

CLK2

Receiving edge arrives before the launching edge

Clock Jitter
Clock jitter refers to the temporal variation of the clock period at a given point that is the clock period can reduce or expand on a cycle-by-cycle basis. It is strictly a temporal uncertainty measure and is often specified at a given point on the chip.

CLK

TC LK

t j itter -tji tte r

In

REGS

Combinat ional Logi c t log ic t log ic, cd

C LK tc-q , tc-q, ts u, thold tjitter

cd

Impact of Skew and Jitter on Performance

Sources of Skew and Jitter

4 Power Supply 3 Interconnect Devices

6 Capacitive Load 7 Coupling to Adjacent Lines

5 Temperature 1 Clock Generation

Clock-Distribution Technique

CLK

Clock is distributed in a tree-like fashion

The Grid System

GCL K Driv er

Driver

Driver

GCLK

GCLK

Driv er GCL K

No re-matching Large power

Synchronizers and Arbiters

fin Asynchronous system Synchronous system fCLK Synchronization

Arbiter: Circuit to decide which of 2 events occurred first Synchronizer: Arbiter with clock f as one of the inputs

A Simple Synchronizer
CLK int I1 Q I2 CLK
Data sampled on rising edge of the clock Latch will eventually resolve the signal value, but ... this might take infinite time!

Arbiters
Req1 Req2 Arbiter Ack1 Req1 Ack2
Ack1

A B
Ack2

(a) Schematic symbol Req1 Req2 A B metastable Ack1 VT gap

Req2

(b) Implementation

(c) Timing diagram

PLL-Based Synchronization
Chip 1 Data Digital System fsystem = N x fcrystal PLL fcrystal , 200<Mhz
Crystal Oscillator reference clock

Chip 2 Digital System

Divider

PLL Clock Buffer

PLL Block Diagram

Reference clock
Up

Phase detector
Down

Charge pump

Loop filter

vcont
VCO

Local clock

Divide by N

System Clock

Mesochronous pipelining scheme

Conventional pipeline system