Digital Electronics

Flip-Flops

Objectives:
Given input logice levels, state the output of an RS

NAND and RS NOR.

Given a clock signal, determine the PGT and NGT. Define Edge Triggered and Level Triggered. Draw a Clocked F/F with and Edge Triggered clock input and a Level Triggered clock input.

LOGIC CIRCUITS
Logic circuits are classified into two groups:
Combinational logic circuits
Basic building blocks include:
Logic gates make decisions

Sequential logic circuits

Flip Flops have memory

Basic building blocks include FLIP-FLOPS:

FLIP-FLOPS
Memory device capable of storing one bit

S R

Q Q

Memory means circuit remains in one state after condition that caused the state is removed. Two outputs designated Q and Q-Not that are always opposite or complimentary. When referring to the state of a flip flop, referring to the state of the Q output.

FLIP-FLOPS
SET RESET
Symbol

S R
R 0 0 1 1

Q Q
MODE Q Invalid RESET Q=0 Q=1 SET No change

To SET a flip flop means to make Q =1

Truth Table
S 0 1 0 1

To RESET a flip flop means to make Q = 0

FLIP-FLOPS
5V +V

OUTPUT Q
NPN

1k 1k 1k 1k 1k 1k

1k

OUTPUT NOT Q
NPN

1k

set input

reset input

The flip flop is a bi-stable multivibrator; it has two stable states. The RS flip flop can be implemented with transistors.

R-S FLIP-FLOP
Symbols:
Set S FF R Q Q Normal

Reset

Complementary

Truth Table:
Mode of Operation Prohibited Set Reset Hold Inputs S R 0 0 1 1 0 1 0 1 Outputs Q Q 1 1 0 Q 1 0 1 Q

NOTE: Active-LOW inputs

R-S FLIP-FLOP Active-Low

NAND LATCH
Q
SET 7400

Q NOT

RESET

7400

DEMORGANIZED NAND LATCH

NA ND LATCH
SET

Q NOT

RESET

SET RES Q NOT-Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 NO CHG

MODE PROHIBITED SET RESET HOLD

ACTIVE-LOW R-S FLIP-FLOP

TIMING DIAGRAMS
S R
S 0 0 1 1 R 0 1 0 1

Q Q

R S Q

MODE Q R Invalid Q=1 SET Q=0 RESET S No change

Q R S Q R S Q

R-S FLIP-FLOP Active-High

SET Normally low RESET

R Latch

Q Q

S R

Q Q

ET

Q Q

Q S Q R

QS Q
R

Q Q

SET

S S 0 0 1 1 0 1 0 1

R 0 0 1 1

R Q Q 0 change change No No Q=1 0 Q=1 Q=0 1 Invalid Q=0 1 Invalid

ACTIVE-HIGH R-S FLIP-FLOP

S R Q Q S 0 1 0 1 R Q 0 No change Q=1 0R 1 Q=0 S 1 Invalid
Q
S 0 1 0 1 R 0 0 1 1 Q No change Q=1 Q=0 Invalid

TIMING DIAGRAMS

R S Q R S Q R S Q

TEST
Memory 1. Logic gates make decisions, flip flops have ____________________?
2. One flip flop can store how many bits? 3. What are the two outputs of a flip flop?

1 Q Q-NOT

4. When referring to the state of a flip flop, were referring to the state of which output?

Q Q=1 Q=0

5. What does it mean to SET a flip flop? 6. What does it mean to RESET a flip flop?

TEST
What is the mode of operation of the R-S flip-flop (set, reset or hold)? What is the output at Q from the R-S flip-flop (active LOW inputs)?
L H

?High
Mode of operation =

Set ?

H H

?High
Mode of operation =

Hold ?

H L

? Low
Mode of operation = ? Reset

CLOCKED R-S FLIP-FLOP

Set
S

FF Q

Set
S Clock

FF Q Q

CLK Reset R Q Reset R

ASYNCHRONOUS Outputs of logic circuit can change state anytime one or more input changes

SYNCHRONOUS Clock signal determines exact time at which any output can change state

Clock Digital signal in the form of a rectangular or square wave

Astable multivibrator

A clocked flip flop changes state only when permitted by the clock signal

TRIGGERING OF FLIP-FLOPS
Level-triggering is the transfer of data from input to output of a flip-flop anytime the clock pulse is proper voltage level. Edge-triggering is the transfer of data from input to output of a flip-flop on the rising edge (L-to-H) or falling edge (H-to-L) of the clock pulse. Edge triggering may be either positive-edge (L-to-H) or negative-edge (H-to-L).
PGT-Positive Going Transition Positive-edge triggering NGT-Negative Going Transition Negative-edge triggering
H time L

Level triggering

CLOCKED R-S FLIP-FLOP

Symbols:
Set S Clock CLK FF Q Q Complementary Normal

Reset

Truth Table:
Mode of operation Hold Reset Set Prohibited Clk Inputs S R 0 0 1 1 0 1 0 1 Outputs Q Q no change 0 1 1 0 0 0

+ pulse + pulse + pulse

NOTE: Active-High inputs

TEST
What is the mode of operation of the clocked R-S flip-flop (set, reset, hold)? What is the output at Q from the clocked R-S flip-flop (active HIGH inputs)?
H ^ L

? High Mode of operation = ? Set

L ^ L

High ?
Mode of operation = ?Hold

L
^ H

? Low Mode of operation = ?Reset

CLOCKED R-S FLIP-FLOP

TIMING DIAGRAMS
Q Q
C 0 1 1 1 1 R X 0 0 1 1

S C R
S X 0 1 0 1

Q
Q No change No change 1 0 Illegal

S 0 1 0 1

R 0 C 0 1 R 1
S Q C R S Q

Q No change Q=1 Q=0 Invalid

Q Q

S C R

S 0 1 0 1

R C 0 0 R 1 1 S
Q

Q No change Q=1 Q=0 Invalid

POSITIVE EDGE TRIGGERED Symbols: R-S FLIP-FLOP

EDGE TRIGGERED R-S FLIP FLOP
SET

CLOCK

Q NOT
RESET

S CLK R

Q Q

Truth Table:

CLK SET RES Q NOT-Q PGT 0 0 NO CHG PGT 0 1 0 1 PGT 1 0 1 0 PGT 1 1 1 1

CLK 0 1

MODE HOLD RESET SET INV ALID

R X X X 0 0 1 1

S X X X 0 1 0 1

Q NO CHG NO CHG NO CHG NO CHG SET RESET ILLEGAL

POSITIVE EDGE TRIGGERED R-S FLIP-FLOP

TIMING DIAGRAMS
S CLK R Q Q

C R
Q

CLK

R 0 0 1 1

S 0 1 0 1

NO CHG SET RESET ILLEGAL

S Q

NEGATIVE EDGE TRIGGERED Symbols: R-S FLIP-FLOP

EDGE TRIGGERED R-S FLIP FLOP
SET

CLOCK

EDGE DETECTOR

Q NOT

S CLK R

Q Q

RESET

Truth Table:

CLK SET RES Q NOT-Q PGT 0 0 NO CHG PGT 0 1 0 1 PGT 1 0 1 0 PGT 1 1 1 1

CLK 0 1

MODE HOLD RESET SET INV ALID

R X X X 0 0 1 1

S X X X 0 1 0 1

Q NO CHG NO CHG NO CHG NO CHG SET RESET ILLEGAL

NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP

TIMING DIAGRAMS
S CLK R Q Q

C R
Q

CLK

R 0 0 1 1

S 0 1 0 1

NO CHG SET RESET ILLEGAL

S Q

TEST
1. Type of flip flop where the outputs of circuit can change state anytime one or more input changes? ASYNCHRONOUS

2. Type of flip flop where the clock signal controls when any output can change state? SYNCHRONOUS

3. What do we call a digital signal in the form of a repetitive pulse or square wave? CLOCK 4. Which is easier to design and troubleshoot, clocked or not clocked flip flops? Clocked flip flops are easier to troubleshoot because we can stop the clock and examine one set of input and output conditions.